include: zephyr: dt-bindings: clock: factorize STM32_* clock source macros

Factorize definitions of the macros used to describe in the STM32
boards device tree the RCC register dedicated to clock source selection
configuration, instead of replicating the macros per SoC header file.
For that purpose, use DT cell bit fields that matches all SoCs.

This change also factorizes STM32_MCO_CFGR_* macros that use the same
packing layout for defining selection of the MCO clocks and for MCO
pre-scaling factor on SoCs that support the feature.

By the way, reorder argument description in macro inline description
comment in a standard way (first argument first).

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Author: etienne-lms

include/zephyr/dt-bindings/clock/stm32_common_clocks.h

@@ -20,35 +20,58 @@
 /** Clock divider */
 #define STM32_CLOCK_DIV(div)	(((div) - 1) << STM32_CLOCK_DIV_SHIFT)
 
-/** STM32 MCO configuration values */
-#define STM32_MCO_CFGR_REG_MASK     0xFFFFU
-#define STM32_MCO_CFGR_REG_SHIFT    0U
-#define STM32_MCO_CFGR_SHIFT_MASK   0x3FU
-#define STM32_MCO_CFGR_SHIFT_SHIFT  16U
-#define STM32_MCO_CFGR_MASK_MASK    0x1FU
-#define STM32_MCO_CFGR_MASK_SHIFT   22U
-#define STM32_MCO_CFGR_VAL_MASK     0x1FU
-#define STM32_MCO_CFGR_VAL_SHIFT    27U
+/** Helper macros to pack RCC clock source selection register info in the DT */
+#define STM32_DT_CLKSEL_REG_MASK	0xFFFFU
+#define STM32_DT_CLKSEL_REG_SHIFT	0U
+#define STM32_DT_CLKSEL_SHIFT_MASK	0x3FU
+#define STM32_DT_CLKSEL_SHIFT_SHIFT	16U
+#define STM32_DT_CLKSEL_MASK_MASK	0x1FU
+#define STM32_DT_CLKSEL_MASK_SHIFT	22U
+#define STM32_DT_CLKSEL_VAL_MASK	0x1FU
+#define STM32_DT_CLKSEL_VAL_SHIFT	27U
 
 /**
- * @brief STM32 MCO configuration register bit field
+ * @brief Pack STM32 source clock selection RCC register bit fields for the DT
  *
- * @param reg    Offset to RCC register holding MCO configuration
- * @param shift    Position of field within RCC register (= field LSB's index)
- * @param mask    Mask of register field in RCC register
- * @param val    Clock configuration field value (0~0x1F)
+ * @param val    Clock configuration field value
+ * @param mask   Mask of register field in RCC register
+ * @param shift  Position of field within RCC register (= field LSB's index)
+ * @param reg    Offset to target clock configuration register in RCC
  *
- * @note 'reg' range:    0x0~0xFFFF    [ 00 : 15 ]
- * @note 'shift' range:    0~63        [ 16 : 21 ]
- * @note 'mask' range:    0x00~0x1F    [ 22 : 26 ]
+ * @note 'reg' range:    0x0~0xFFFF   [ 00 : 15 ]
+ * @note 'shift' range:  0~63         [ 16 : 21 ]
+ * @note 'mask' range:   0x00~0x1F    [ 22 : 26 ]
  * @note 'val' range:    0x00~0x1F    [ 27 : 31 ]
- *
  */
-#define STM32_MCO_CFGR(val, mask, shift, reg)                        \
-	((((reg) & STM32_MCO_CFGR_REG_MASK) << STM32_MCO_CFGR_REG_SHIFT) |        \
-	 (((shift) & STM32_MCO_CFGR_SHIFT_MASK) << STM32_MCO_CFGR_SHIFT_SHIFT) |    \
-	 (((mask) & STM32_MCO_CFGR_MASK_MASK) << STM32_MCO_CFGR_MASK_SHIFT) |        \
-	 (((val) & STM32_MCO_CFGR_VAL_MASK) << STM32_MCO_CFGR_VAL_SHIFT))
+#define STM32_DT_CLOCK_SELECT(val, mask, shift, reg)					\
+	((((reg) & STM32_DT_CLKSEL_REG_MASK) << STM32_DT_CLKSEL_REG_SHIFT) |		\
+	 (((shift) & STM32_DT_CLKSEL_SHIFT_MASK) << STM32_DT_CLKSEL_SHIFT_SHIFT) |	\
+	 (((mask) & STM32_DT_CLKSEL_MASK_MASK) << STM32_DT_CLKSEL_MASK_SHIFT) |		\
+	 (((val) & STM32_DT_CLKSEL_VAL_MASK) << STM32_DT_CLKSEL_VAL_SHIFT))
+
+/* STM32_CLOCK_* macros, defined for convenience */
+#define STM32_CLOCK_REG_MASK		STM32_DT_CLKSEL_REG_MASK
+#define STM32_CLOCK_REG_SHIFT		STM32_DT_CLKSEL_REG_SHIFT
+#define STM32_CLOCK_SHIFT_MASK		STM32_DT_CLKSEL_SHIFT_MASK
+#define STM32_CLOCK_SHIFT_SHIFT		STM32_DT_CLKSEL_SHIFT_SHIFT
+#define STM32_CLOCK_MASK_MASK		STM32_DT_CLKSEL_MASK_MASK
+#define STM32_CLOCK_MASK_SHIFT		STM32_DT_CLKSEL_MASK_SHIFT
+#define STM32_CLOCK_VAL_MASK		STM32_DT_CLKSEL_VAL_MASK
+#define STM32_CLOCK_VAL_SHIFT		STM32_DT_CLKSEL_VAL_SHIFT
+#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \
+	STM32_DT_CLOCK_SELECT((val), (mask), (shift), (reg))
+
+/* STM32_MCO_CFGR_* macros, defined for convenience */
+#define STM32_MCO_CFGR_REG_MASK		STM32_DT_CLKSEL_REG_MASK
+#define STM32_MCO_CFGR_REG_SHIFT	STM32_DT_CLKSEL_REG_SHIFT
+#define STM32_MCO_CFGR_SHIFT_MASK	STM32_DT_CLKSEL_SHIFT_MASK
+#define STM32_MCO_CFGR_SHIFT_SHIFT	STM32_DT_CLKSEL_SHIFT_SHIFT
+#define STM32_MCO_CFGR_MASK_MASK	STM32_DT_CLKSEL_MASK_MASK
+#define STM32_MCO_CFGR_MASK_SHIFT	STM32_DT_CLKSEL_MASK_SHIFT
+#define STM32_MCO_CFGR_VAL_MASK		STM32_DT_CLKSEL_VAL_MASK
+#define STM32_MCO_CFGR_VAL_SHIFT	STM32_DT_CLKSEL_VAL_SHIFT
+#define STM32_MCO_CFGR(val, mask, shift, reg)	\
+	STM32_DT_CLOCK_SELECT((val), (mask), (shift), (reg))
 
 /**
  * Pack RCC clock register offset and bit in two 32-bit values

include/zephyr/dt-bindings/clock/stm32c0_clock.h

@@ -29,34 +29,6 @@
 /** Peripheral bus clock */
 #define STM32_SRC_PCLK		(STM32_SRC_HSE + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x54
 

include/zephyr/dt-bindings/clock/stm32f0_clock.h

@@ -30,34 +30,6 @@
 /** PLL clock */
 #define STM32_SRC_PLLCLK	(STM32_SRC_PCLK + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CFGRx register offset
- * @param shift Position within RCC_CFGRx.
- * @param mask Mask for the RCC_CFGRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CFGRx register offset */
 #define CFGR1_REG               0x04
 #define CFGR3_REG		0x30

include/zephyr/dt-bindings/clock/stm32f1_clock.h

@@ -28,34 +28,6 @@
 #define STM32_SRC_EXT_HSE       (STM32_SRC_HSE + 1)
 #define STM32_SRC_PLLCLK        (STM32_SRC_EXT_HSE + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CFGRx register offset
- * @param shift Position within RCC_CFGRx.
- * @param mask Mask for the RCC_CFGRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CFGRx register offset */
 #define CFGR1_REG               0x04
 #define CFGR2_REG		0x2C

include/zephyr/dt-bindings/clock/stm32f3_clock.h

@@ -31,34 +31,6 @@
 /** PLL clock */
 #define STM32_SRC_PLLCLK	(STM32_SRC_PCLK + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CFGRx register offset
- * @param shift Position within RCC_CFGRx.
- * @param mask Mask for the RCC_CFGRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CFGRx register offset */
 #define CFGR_REG		0x04
 #define CFGR3_REG		0x30

include/zephyr/dt-bindings/clock/stm32f4_clock.h

@@ -43,34 +43,6 @@
 /* I2S_CKIN not supported yet */
 /* #define STM32_SRC_I2S_CKIN	TBD */
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CFGRx register offset
- * @param shift Position within RCC_CFGRx.
- * @param mask Mask for the RCC_CFGRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)                                                  \
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |                               \
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |                         \
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |                            \
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CFGRx register offset */
 #define CFGR_REG 0x08
 /** @brief RCC_BDCR register offset */

include/zephyr/dt-bindings/clock/stm32f7_clock.h

@@ -40,35 +40,6 @@
 
 #define STM32_SRC_PLLI2S_R      (STM32_SRC_PCLK + 1)
 
-
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CFGRx register offset
- * @param shift Position within RCC_CFGRx.
- * @param mask Mask for the RCC_CFGRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CFGRx register offset */
 #define CFGR_REG		0x08
 

include/zephyr/dt-bindings/clock/stm32g0_clock.h

@@ -35,34 +35,6 @@
 #define STM32_SRC_PLL_Q		(STM32_SRC_PLL_P + 1)
 #define STM32_SRC_PLL_R		(STM32_SRC_PLL_Q + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x54
 #define CCIPR2_REG		0x58

include/zephyr/dt-bindings/clock/stm32g4_clock.h

@@ -39,34 +39,6 @@
 #define STM32_SRC_PLL_R		(STM32_SRC_PLL_Q + 1)
 /* TODO: PLLSAI clocks */
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x88
 #define CCIPR2_REG		0x9C

include/zephyr/dt-bindings/clock/stm32h5_clock.h

@@ -51,34 +51,6 @@
 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB1
 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB3
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32H5 clock configuration bit field.
- *
- * - reg   (1/2/3/4/5)     [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |	\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |	\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPRx register offset (RM0456.pdf) */
 #define CCIPR1_REG		0xD8
 #define CCIPR2_REG		0xDC