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drivers: gpio: add amebadplus gpio driver
GPIO driver for amebadplus Signed-off-by: zjian zhang <zjian_zhang@realsil.com.cn>
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‎drivers/gpio/CMakeLists.txt

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@@ -10,6 +10,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_ADP5585 gpio_adp5585.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ADS1X4S0X gpio_ads1x4s0x.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ALTERA_PIO gpio_altera_pio.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_AMBIQ gpio_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_AMEBA gpio_ameba.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ANDES_ATCGPIO100 gpio_andes_atcgpio100.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_AW9523B gpio_aw9523b.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_AXP192 gpio_axp192.c)

‎drivers/gpio/Kconfig

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@@ -201,4 +201,6 @@ source "drivers/gpio/Kconfig.xlnx_ps"
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source "drivers/gpio/Kconfig.xmc4xxx"
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# zephyr-keep-sorted-stop
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source "drivers/gpio/Kconfig.ameba"
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endif # GPIO

‎drivers/gpio/Kconfig.ameba

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# Copyright (c) 2024 Realtek Semiconductor Corp.
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_AMEBA
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bool "GPIO controller driver for Realtek Ameba series SoC"
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default y
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depends on DT_HAS_REALTEK_AMEBA_GPIO_ENABLED
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help
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Enable GPIO controller driver for Realtek Ameba series SoC
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config GPIO_DEBOUNCE_EN
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bool "Ameba GPIO Interrupt Debounce Enable"
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depends on GPIO_AMEBA
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default y
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help
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When Enable GPIO Interrupt Debounce, the external signal can be debounced to
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remove any spurious glitches that are less than one period(about 32us) of
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the external debouncing clock.

‎drivers/gpio/gpio_ameba.c

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/*
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* Copyright (c) 2024 Realtek Semiconductor Corp.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT realtek_ameba_gpio
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/* Include <soc.h> before <ameba_soc.h> to avoid redefining unlikely() macro */
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#include <soc.h>
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#include <ameba_soc.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(gpio_ameba, CONFIG_GPIO_LOG_LEVEL);
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#define GPIO_PINNAME(PORT, PIN) (((PORT) << 5) | ((PIN) & 0x1F))
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struct gpio_ameba_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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/* port base address */
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uint32_t base;
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/* IO port */
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int port;
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};
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struct gpio_ameba_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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};
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static int gpio_ameba_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_ameba_config *cfg = dev->config;
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*value = GPIO_PortRead(cfg->port, cfg->common.port_pin_mask);
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return 0;
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}
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static int gpio_ameba_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value)
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{
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const struct gpio_ameba_config *cfg = dev->config;
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GPIO_PortDirection(cfg->port, mask, GPIO_Mode_OUT);
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GPIO_PortWrite(cfg->port, mask, value);
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return 0;
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}
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static int gpio_ameba_port_set_bits_raw(const struct device *dev, uint32_t mask)
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{
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const struct gpio_ameba_config *cfg = dev->config;
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GPIO_PortWrite(cfg->port, mask, cfg->common.port_pin_mask);
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return 0;
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}
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static int gpio_ameba_port_clear_bits_raw(const struct device *dev, uint32_t mask)
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{
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const struct gpio_ameba_config *cfg = dev->config;
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GPIO_PortWrite(cfg->port, mask, 0);
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return 0;
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}
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static int gpio_ameba_port_toggle_bits(const struct device *dev, uint32_t mask)
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{
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const struct gpio_ameba_config *cfg = dev->config;
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u32 gpio_pin;
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u32 value;
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uint8_t i;
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for (i = 0; i < 32; i++) {
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if (mask & 0x1) {
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gpio_pin = GPIO_PINNAME(cfg->port, i);
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value = GPIO_ReadDataBit(gpio_pin);
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GPIO_WriteBit(gpio_pin, (~value) & 0x1);
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}
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mask >>= 1;
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if (mask == 0) {
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break;
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}
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}
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return 0;
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}
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static int gpio_ameba_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_ameba_config *cfg = dev->config;
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GPIO_InitTypeDef gpio_initstruct;
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u32 gpio_pin;
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == 0) {
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return -ENOTSUP;
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}
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gpio_pin = GPIO_PINNAME(cfg->port, pin);
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gpio_initstruct.GPIO_Pin = gpio_pin;
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if (flags & GPIO_INPUT) {
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gpio_initstruct.GPIO_Mode = GPIO_Mode_IN;
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} else {
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gpio_initstruct.GPIO_Mode = GPIO_Mode_OUT;
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}
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if (flags & GPIO_PULL_UP) {
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gpio_initstruct.GPIO_PuPd = GPIO_PuPd_UP;
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} else if (flags & GPIO_PULL_DOWN) {
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gpio_initstruct.GPIO_PuPd = GPIO_PuPd_DOWN;
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} else {
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gpio_initstruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
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}
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GPIO_Init(&gpio_initstruct);
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if (flags & GPIO_OUTPUT) {
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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gpio_ameba_port_set_bits_raw(dev, BIT(pin));
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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gpio_ameba_port_clear_bits_raw(dev, BIT(pin));
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}
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}
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return 0;
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}
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static int gpio_ameba_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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const struct gpio_ameba_config *cfg = dev->config;
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u32 gpio_pin;
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gpio_pin = GPIO_PINNAME(cfg->port, pin);
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GPIO_InitTypeDef gpio_initstruct;
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gpio_initstruct.GPIO_Pin = gpio_pin;
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GPIO_INTConfig(gpio_pin, DISABLE);
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LOG_DBG("Config GPIO int:%d-%d, mode:%x, flag:0x%x\n", cfg->port, pin, mode, trig);
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gpio_initstruct.GPIO_Pin = gpio_pin;
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gpio_initstruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
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gpio_initstruct.GPIO_Mode = GPIO_Mode_INT;
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gpio_initstruct.GPIO_ITDebounce = GPIO_INT_DEBOUNCE_DISABLE;
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if (mode != GPIO_INT_MODE_DISABLED) {
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if (mode & GPIO_INT_MODE_EDGE) {
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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gpio_initstruct.GPIO_ITTrigger = GPIO_INT_Trigger_EDGE;
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gpio_initstruct.GPIO_ITPolarity = GPIO_INT_POLARITY_ACTIVE_LOW;
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break;
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case GPIO_INT_TRIG_HIGH:
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gpio_initstruct.GPIO_ITTrigger = GPIO_INT_Trigger_EDGE;
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gpio_initstruct.GPIO_ITPolarity = GPIO_INT_POLARITY_ACTIVE_HIGH;
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break;
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case GPIO_INT_TRIG_BOTH:
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gpio_initstruct.GPIO_ITTrigger = GPIO_INT_Trigger_BOTHEDGE;
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break;
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default:
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LOG_ERR("GPIO Edge interrupt type invalid \r\n");
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return -ENOTSUP;
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}
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} else {
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gpio_initstruct.GPIO_ITTrigger = GPIO_INT_Trigger_LEVEL;
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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gpio_initstruct.GPIO_ITPolarity = GPIO_INT_POLARITY_ACTIVE_LOW;
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gpio_initstruct.GPIO_PuPd = GPIO_PuPd_UP;
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break;
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case GPIO_INT_TRIG_HIGH:
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gpio_initstruct.GPIO_ITPolarity = GPIO_INT_POLARITY_ACTIVE_HIGH;
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gpio_initstruct.GPIO_PuPd = GPIO_PuPd_DOWN;
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break;
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default:
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LOG_ERR("GPIO level interrupt doesn't support both high and low");
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return -ENOTSUP;
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}
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}
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#if defined(CONFIG_GPIO_DEBOUNCE_EN)
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gpio_initstruct.GPIO_ITDebounce = GPIO_INT_DEBOUNCE_ENABLE;
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/* GPIO_DebounceClock(cfg->port, DEBOUNCE_DIV_CNT); */
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GPIO_Init(&gpio_initstruct);
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DelayUs(64);
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GPIO_INTConfig(gpio_pin, ENABLE);
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#else
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GPIO_Init(&gpio_initstruct);
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GPIO_INTConfig(gpio_pin, ENABLE);
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#endif
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} else {
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GPIO_Direction(gpio_pin, GPIO_Mode_IN);
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PAD_PullCtrl(gpio_pin, gpio_initstruct.GPIO_PuPd);
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GPIO_INTMode(gpio_pin, DISABLE, 0, 0, 0);
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}
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return 0;
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}
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static int gpio_ameba_manage_callback(const struct device *dev, struct gpio_callback *callback,
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bool set)
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{
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struct gpio_ameba_data *data = dev->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static uint32_t gpio_ameba_get_pending_int(const struct device *dev)
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{
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uint32_t irq_status;
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const struct gpio_ameba_config *cfg = dev->config;
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uint32_t port = cfg->port;
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irq_status = GPIO_INTStatusGet(port);
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return irq_status;
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}
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static void gpio_ameba_isr(const struct device *dev)
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{
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uint32_t int_status;
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struct gpio_ameba_data *data = dev->data;
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const struct gpio_ameba_config *cfg = dev->config;
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uint32_t port = cfg->port;
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/* Get the int status */
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int_status = GPIO_INTStatusGet(port);
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/* Clear pending edge interrupt */
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GPIO_INTStatusClearEdge(port);
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/* Call the registered callbacks */
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gpio_fire_callbacks(&data->callbacks, dev, int_status);
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}
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static const struct gpio_driver_api gpio_ameba_driver_api = {
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.pin_configure = gpio_ameba_configure,
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.port_get_raw = gpio_ameba_port_get_raw,
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.port_set_masked_raw = gpio_ameba_port_set_masked_raw,
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.port_set_bits_raw = gpio_ameba_port_set_bits_raw,
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.port_clear_bits_raw = gpio_ameba_port_clear_bits_raw,
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.port_toggle_bits = gpio_ameba_port_toggle_bits,
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.pin_interrupt_configure = gpio_ameba_pin_interrupt_configure,
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.manage_callback = gpio_ameba_manage_callback,
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.get_pending_int = gpio_ameba_get_pending_int,
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};
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#define GPIO_AMEBA_INIT(n) \
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static int gpio_ameba_port##n##_init(const struct device *dev) \
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{ \
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const struct gpio_ameba_config *cfg = dev->config; \
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LOG_INF("GPIO%d INIT, IRQ %d\n", cfg->port, DT_INST_IRQN(n)); \
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\
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), gpio_ameba_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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\
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return 0; \
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} \
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static struct gpio_ameba_data gpio_ameba_port##n##_data; \
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\
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static const struct gpio_ameba_config gpio_ameba_port##n##_config = { \
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.common = \
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{ \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.base = DT_INST_REG_ADDR(n), \
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.port = n, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, gpio_ameba_port##n##_init, NULL, &gpio_ameba_port##n##_data, \
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&gpio_ameba_port##n##_config, POST_KERNEL, \
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CONFIG_GPIO_INIT_PRIORITY, &gpio_ameba_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(GPIO_AMEBA_INIT)

‎dts/bindings/gpio/realtek,ameba-gpio.yaml

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# Copyright (c) 2024 Realtek Semiconductor Corp.
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# SPDX-License-Identifier: Apache-2.0
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description: Realtek Ameba GPIO controller
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compatible: "realtek,ameba-gpio"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags

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