drivers: timer: Add timer driver for or1k

The OpenRISC 1000 Tick Timer is tightly coupled to the or1k CPU core, and
is explicitly designed to facilitate task scheduling and high-resolution
timing.

The timer is documented in Chapter 14 of the OpenRISC 1000 Architecture
Manual:

    https://openrisc.io/or1k.html#__RefHeading__504849_595890882

Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>

Author: jhol

MAINTAINERS.yml

@@ -5576,6 +5576,7 @@ OpenRISC Arch:
     - jhol
   files:
     - arch/openrisc/
+    - drivers/timer/*openrisc*
     - include/zephyr/arch/openrisc/
   labels:
     - "area: OpenRISC"

drivers/timer/CMakeLists.txt

@@ -30,6 +30,7 @@ zephyr_library_sources_ifdef(CONFIG_NATIVE_POSIX_TIMER native_posix_timer.c)
 zephyr_library_sources_ifdef(CONFIG_NPCX_ITIM_TIMER npcx_itim_timer.c)
 zephyr_library_sources_ifdef(CONFIG_NRF_GRTC_TIMER nrf_grtc_timer.c)
 zephyr_library_sources_ifdef(CONFIG_NRF_RTC_TIMER nrf_rtc_timer.c)
+zephyr_library_sources_ifdef(CONFIG_OPENRISC_TICK_TIMER openrisc_tick_timer.c)
 zephyr_library_sources_ifdef(CONFIG_RCAR_CMT_TIMER rcar_cmt_timer.c)
 zephyr_library_sources_ifdef(CONFIG_RISCV_MACHINE_TIMER riscv_machine_timer.c)
 zephyr_library_sources_ifdef(CONFIG_RV32M1_LPTMR_TIMER rv32m1_lptmr_timer.c)

drivers/timer/Kconfig

@@ -88,6 +88,7 @@ source "drivers/timer/Kconfig.npcx_itim"
 source "drivers/timer/Kconfig.nrf_rtc"
 source "drivers/timer/Kconfig.nrf_grtc"
 source "drivers/timer/Kconfig.nrf_xrtc"
+source "drivers/timer/Kconfig.openrisc_tick"
 source "drivers/timer/Kconfig.rcar_cmt"
 source "drivers/timer/Kconfig.riscv_machine"
 source "drivers/timer/Kconfig.rv32m1_lptmr"

drivers/timer/Kconfig.openrisc_tick

@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config OPENRISC_TICK_TIMER
+	bool "OpenRISC Tick Timer"
+	depends on OPENRISC
+	select TICKLESS_CAPABLE
+	help
+	  This module implements a kernel device driver for the OpenRISC Tick timer.

drivers/timer/openrisc_tick_timer.c

@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2025 NVIDIA Corporation <jholdsworth@nvidia.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/timer/system_timer.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/spinlock.h>
+#include <zephyr/sys_clock.h>
+
+#include <openrisc/openriscregs.h>
+
+#define MAX_CYC SPR_TTMR_TP
+
+static struct k_spinlock lock;
+static uint32_t last_count;
+static uint64_t last_ticks;
+static uint32_t last_elapsed;
+static uint32_t cyc_per_tick;
+
+static ALWAYS_INLINE void set_compare(uint32_t time)
+{
+	openrisc_write_spr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_CR | time);
+}
+
+static ALWAYS_INLINE void clear_compare(void)
+{
+	openrisc_write_spr(SPR_TTMR, SPR_TTMR_CR);
+}
+
+static ALWAYS_INLINE uint32_t get_count(void)
+{
+	return openrisc_read_spr(SPR_TTCR);
+}
+
+void z_openrisc_timer_isr(void)
+{
+	if (IS_ENABLED(CONFIG_TRACING_ISR)) {
+		sys_trace_isr_enter();
+	}
+
+	const k_spinlock_key_t key = k_spin_lock(&lock);
+
+	const uint32_t current_count = get_count();
+	const uint32_t delta_count = current_count - last_count;
+	const uint32_t delta_ticks = delta_count / cyc_per_tick;
+
+	last_count += delta_ticks * cyc_per_tick;
+	last_ticks += delta_ticks;
+	last_elapsed = 0;
+
+	if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+		clear_compare();
+	} else {
+		set_compare((last_count + cyc_per_tick) & MAX_CYC);
+	}
+
+	k_spin_unlock(&lock, key);
+	sys_clock_announce(delta_ticks);
+
+	if (IS_ENABLED(CONFIG_TRACING_ISR)) {
+		sys_trace_isr_exit();
+	}
+}
+
+void sys_clock_set_timeout(int32_t ticks, bool idle)
+{
+#if defined(CONFIG_TICKLESS_KERNEL)
+	if (ticks == K_TICKS_FOREVER) {
+		if (idle) {
+			return;
+		}
+
+		ticks = INT32_MAX;
+	}
+
+	/*
+	 * Clamp the max period length to a number of cycles that can fit
+	 * in half the range of a cycle_diff_t for native width divisions
+	 * to be usable elsewhere. The half range gives us extra room to cope
+	 * with the unavoidable IRQ servicing latency.
+	 */
+	ticks = CLAMP(ticks, 0, MAX_CYC / 2 / cyc_per_tick);
+
+	const uint32_t compare =
+		((last_ticks + last_elapsed + (uint32_t)ticks) * cyc_per_tick) & MAX_CYC;
+	const k_spinlock_key_t key = k_spin_lock(&lock);
+
+	set_compare(compare);
+	k_spin_unlock(&lock, key);
+
+#else  /* CONFIG_TICKLESS_KERNEL */
+	ARG_UNUSED(ticks);
+	ARG_UNUSED(idle);
+#endif
+}
+
+uint32_t sys_clock_elapsed(void)
+{
+	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+		return 0;
+	}
+
+	const k_spinlock_key_t key = k_spin_lock(&lock);
+
+	const uint32_t current_count = get_count();
+	const uint32_t delta_count = current_count - last_count;
+	const uint32_t delta_ticks = delta_count / cyc_per_tick;
+
+	last_elapsed = delta_ticks;
+	k_spin_unlock(&lock, key);
+	return delta_ticks;
+}
+
+uint32_t sys_clock_cycle_get_32(void)
+{
+	return get_count();
+}
+
+static int sys_clock_driver_init(void)
+{
+	cyc_per_tick = (uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec() /
+		(uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC);
+
+	last_ticks = get_count() / cyc_per_tick;
+	last_count = last_ticks * cyc_per_tick;
+	last_elapsed = 0;
+
+	set_compare((last_count + cyc_per_tick) & MAX_CYC);
+
+	return 0;
+}
+
+SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
+	 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);