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drivers: ethernet: phy: Add Intel IGC PHY driver
Intel IGC(aka Foxville) is a fully integrated MAC and PHY. This commit adds support for the Intel IGC PHY driver with the following features: - Support 10/100/1000 BASE-T. - Auto Negotiation for 10/100/1000 Mbps speeds. - Integration with the MDIO interface for PHY register access. - Device tree support for PHY configuration and initialization. It uses the MDIO interface to communicate with the PHY and supports modular configuration via the device tree. Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Signed-off-by: Ling Pei Lee <pei.lee.ling@intel.com>
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‎drivers/ethernet/phy/CMakeLists.txt

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@@ -5,6 +5,7 @@ zephyr_library_sources_ifdef(CONFIG_PHY_GENERIC_MII phy_mii.c)
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# zephyr-keep-sorted-start
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zephyr_library_sources_ifdef(CONFIG_PHY_ADIN2111 phy_adin2111.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_DM8806 phy_dm8806.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_INTEL_IGC phy_intel_igc.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_KSZ8081 phy_microchip_ksz8081.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_T1S phy_microchip_t1s.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_VSC8541 phy_microchip_vsc8541.c)

‎drivers/ethernet/phy/Kconfig

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@@ -122,4 +122,12 @@ config PHY_VERIFY_DEVICE_IDENTIFICATION
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Verify the organizationally unique identifier that is reported
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by the phy chip.
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config PHY_INTEL_IGC
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bool "Intel IGC PHY driver"
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default y
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depends on DT_HAS_INTEL_IGC_PHY_ENABLED
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depends on MDIO_INTEL_IGC
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help
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Enable Intel IGC PHY driver.
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endif # "Ethernet PHY Drivers"

‎drivers/ethernet/phy/phy_intel_igc.c

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/*
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* Copyright (c) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT intel_igc_phy
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/mdio.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/net/phy.h>
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#include <zephyr/net/mii.h>
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#include <zephyr/drivers/ethernet/eth_intel_plat.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(intel_igc_phy, CONFIG_PHY_LOG_LEVEL);
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/* MULTI GBT AN Control Register */
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#define ANEG_MGBT_AN_CTRL_REG 0x20
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#define ADVERTISE_2P5G BIT(7)
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#define ANEG_MMD_DEV_NUM 7
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#define PHY_REV_MASK GENMASK(31, 4)
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#define MII_INVALID_PHY_ID UINT32_MAX
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#define PHY_ID_SHIFT 16
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struct phy_intel_igc_cfg {
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const struct device *const mdio;
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uint8_t phy_addr;
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bool multi_gb_supported;
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};
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struct phy_intel_igc_data {
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const struct device *dev;
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struct phy_link_state state;
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uint32_t phy_id;
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};
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static int phy_intel_igc_read(const struct device *dev, uint16_t reg_addr, uint32_t *value)
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{
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const struct phy_intel_igc_cfg *const cfg = dev->config;
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return mdio_read(cfg->mdio, cfg->phy_addr, reg_addr, (uint16_t *)value);
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}
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static int phy_intel_igc_write(const struct device *dev, uint16_t reg_addr, uint32_t value)
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{
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const struct phy_intel_igc_cfg *const cfg = dev->config;
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return mdio_write(cfg->mdio, cfg->phy_addr, reg_addr, (uint16_t)value);
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}
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static int phy_intel_igc_await_phy_status(const struct device *dev, uint16_t reg_addr,
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uint16_t mask, uint32_t *value, uint16_t delay)
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{
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uint32_t timeout;
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for (timeout = 0U; timeout < CONFIG_PHY_AUTONEG_TIMEOUT_MS; timeout += delay) {
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if (phy_intel_igc_read(dev, reg_addr, value) >= 0) {
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if ((*value & mask) == mask) {
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return 0;
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}
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}
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k_msleep(delay);
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}
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return -ETIMEDOUT;
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}
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static int phy_intel_igc_get_link_state(const struct device *dev,
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struct phy_link_state *state)
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{
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const struct phy_intel_igc_cfg *const cfg = dev->config;
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uint32_t value = 0;
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int ret;
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ret = phy_intel_igc_await_phy_status(dev, MII_BMSR,
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MII_BMSR_LINK_STATUS, &value, 10);
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if (ret < 0) {
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LOG_INF("Get PHY (%d) Status Timed Out", cfg->phy_addr);
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state->is_up = false;
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} else {
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state->is_up = (value & MII_BMSR_LINK_STATUS) ? true : false;
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}
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LOG_INF("PHY (%d) Link %s", cfg->phy_addr, state->is_up ? "Up" : "Down");
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return ret;
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}
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static int phy_intel_igc_restart_aneg(const struct device *dev)
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{
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uint32_t value = 0;
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int ret;
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ret = phy_intel_igc_read(dev, MII_BMCR, &value);
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if (ret < 0) {
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return ret;
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}
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/* Enable Autoneg and Autoneg-restart */
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value |= MII_BMCR_AUTONEG_ENABLE | MII_BMCR_AUTONEG_RESTART;
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ret = phy_intel_igc_write(dev, MII_BMCR, value);
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if (ret < 0) {
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return ret;
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}
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ret = phy_intel_igc_await_phy_status(dev, MII_BMSR,
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MII_BMSR_AUTONEG_COMPLETE, &value, 100);
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if (ret < 0) {
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return ret;
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}
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return 0;
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}
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static int phy_intel_igc_cfg_link(const struct device *dev, enum phy_link_speed speed)
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{
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uint32_t mii_1ktcr_val = 0;
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uint32_t mii_anar_val = 0;
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int ret = 0;
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if ((phy_intel_igc_read(dev, MII_ANAR, &mii_anar_val) < 0) ||
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(phy_intel_igc_read(dev, MII_1KTCR, &mii_1ktcr_val) < 0)) {
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return -EIO;
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}
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if (speed & LINK_HALF_10BASE_T) {
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mii_anar_val |= MII_ADVERTISE_10_HALF;
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} else {
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mii_anar_val &= ~MII_ADVERTISE_10_HALF;
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}
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if (speed & LINK_FULL_10BASE_T) {
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mii_anar_val |= MII_ADVERTISE_10_FULL;
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} else {
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mii_anar_val &= ~MII_ADVERTISE_10_FULL;
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}
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if (speed & LINK_HALF_100BASE_T) {
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mii_anar_val |= MII_ADVERTISE_100_HALF;
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} else {
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mii_anar_val &= ~MII_ADVERTISE_100_HALF;
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}
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if (speed & LINK_FULL_100BASE_T) {
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mii_anar_val |= MII_ADVERTISE_100_FULL;
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} else {
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mii_anar_val &= ~MII_ADVERTISE_100_FULL;
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}
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ret = phy_intel_igc_write(dev, MII_ANAR, mii_anar_val);
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if (ret < 0) {
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return ret;
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}
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if (speed & LINK_FULL_1000BASE_T) {
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mii_1ktcr_val |= MII_ADVERTISE_1000_FULL;
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} else {
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mii_1ktcr_val &= ~MII_ADVERTISE_1000_FULL;
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}
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ret = phy_intel_igc_write(dev, MII_1KTCR, mii_1ktcr_val);
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if (ret < 0) {
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return ret;
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}
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ret = phy_intel_igc_restart_aneg(dev);
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if (ret < 0) {
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return ret;
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}
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return ret;
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}
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static int phy_intel_igc_aneg_10_100mbps(const struct device *dev)
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{
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uint32_t value = 0;
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int ret = 0;
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ret = phy_intel_igc_read(dev, MII_ANAR, &value);
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if (ret < 0) {
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return ret;
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}
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/* Configure 10/100 Mbps advertise */
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value |= MII_ADVERTISE_10_HALF | MII_ADVERTISE_100_HALF |
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MII_ADVERTISE_10_FULL | MII_ADVERTISE_100_FULL;
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/* Disable Flow control (Rx & Tx) */
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value &= ~(MII_ADVERTISE_PAUSE | MII_ADVERTISE_ASYM_PAUSE);
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ret = phy_intel_igc_write(dev, MII_ANAR, value);
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if (ret < 0) {
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return ret;
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}
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return ret;
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}
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static int phy_intel_igc_aneg_1gbps(const struct device *dev)
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{
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uint32_t value = 0;
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int ret = 0;
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ret = phy_intel_igc_read(dev, MII_1KTCR, &value);
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if (ret < 0) {
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return ret;
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}
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/* Configure 1000 Mbps advertise */
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ret = phy_intel_igc_read(dev, MII_1KTCR, &value);
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if (ret < 0) {
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return ret;
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}
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value &= ~MII_ADVERTISE_1000_HALF;
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value |= MII_ADVERTISE_1000_FULL;
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ret = phy_intel_igc_write(dev, MII_1KTCR, value);
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if (ret < 0) {
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return ret;
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}
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return ret;
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}
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static int phy_intel_igc_aneg_multigb(const struct device *dev)
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{
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const struct phy_intel_igc_cfg *cfg = dev->config;
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uint16_t value = 0;
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int ret = 0;
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/* Configure Multi Gigabit advertise */
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ret = mdio_read_c45(cfg->mdio, cfg->phy_addr, ANEG_MMD_DEV_NUM,
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ANEG_MGBT_AN_CTRL_REG, &value);
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if (ret < 0) {
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return ret;
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}
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if (cfg->multi_gb_supported) {
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value |= ADVERTISE_2P5G;
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} else {
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value &= ~ADVERTISE_2P5G;
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}
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ret = mdio_write_c45(cfg->mdio, cfg->phy_addr, ANEG_MMD_DEV_NUM,
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ANEG_MGBT_AN_CTRL_REG, value);
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if (ret < 0) {
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return ret;
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}
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return ret;
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}
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static int phy_intel_igc_id_read(const struct device *dev)
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{
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const struct phy_intel_igc_cfg *cfg = dev->config;
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struct phy_intel_igc_data *data = dev->data;
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uint32_t value = 0;
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int ret = 0;
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ret = phy_intel_igc_read(dev, MII_PHYID1R, &value);
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if (ret < 0) {
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return ret;
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}
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data->phy_id = value << PHY_ID_SHIFT;
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ret = phy_intel_igc_read(dev, MII_PHYID2R, &value);
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if (ret < 0) {
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return ret;
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}
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data->phy_id |= (value & PHY_REV_MASK);
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if (data->phy_id == MII_INVALID_PHY_ID) {
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LOG_ERR("Invalid PHY ID (%d) found at address (%d)",
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data->phy_id, cfg->phy_addr);
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return -EINVAL;
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}
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LOG_INF("PHY ID = 0x%x", data->phy_id);
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return 0;
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}
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static int phy_intel_igc_init(const struct device *dev)
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{
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int ret;
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ret = phy_intel_igc_id_read(dev);
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if (ret < 0) {
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LOG_ERR("Failed to read PHY ID");
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return ret;
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}
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ret = phy_intel_igc_aneg_10_100mbps(dev);
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if (ret < 0) {
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LOG_ERR("Failed to config Autoneg 10/100 Mbps");
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return ret;
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}
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ret = phy_intel_igc_aneg_1gbps(dev);
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if (ret < 0) {
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LOG_ERR("Failed to config Autoneg 1Gbps");
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return ret;
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}
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ret = phy_intel_igc_aneg_multigb(dev);
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if (ret < 0) {
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LOG_ERR("Failed to config Autoneg Multi-Gigabit");
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return ret;
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}
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ret = phy_intel_igc_restart_aneg(dev);
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if (ret < 0) {
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LOG_ERR("Failed to restart Autonegotiation");
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}
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return ret;
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}
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static const struct ethphy_driver_api phy_api = {
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.get_link = phy_intel_igc_get_link_state,
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.cfg_link = phy_intel_igc_cfg_link,
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.read = phy_intel_igc_read,
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.write = phy_intel_igc_write,
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};
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#define INTEL_IGC_PHY_CONFIG(n) \
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static const struct phy_intel_igc_cfg phy_cfg_##n = { \
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.mdio = DEVICE_DT_GET(DT_INST_PARENT(n)), \
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.phy_addr = DT_INST_REG_ADDR(n), \
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.multi_gb_supported = DT_INST_PROP(n, multi_gigabit_support), \
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};
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#define INTEL_IGC_PHY_INIT(n) \
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INTEL_IGC_PHY_CONFIG(n); \
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static struct phy_intel_igc_data phy_data_##n; \
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\
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DEVICE_DT_INST_DEFINE(n, &phy_intel_igc_init, NULL, \
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&phy_data_##n, &phy_cfg_##n, \
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POST_KERNEL, CONFIG_PHY_INIT_PRIORITY, &phy_api);
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DT_INST_FOREACH_STATUS_OKAY(INTEL_IGC_PHY_INIT)

‎dts/bindings/ethernet/intel,igc-phy.yaml

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# Copyright (c) 2025 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Intel IGC PHY documentation.
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compatible: "intel,igc-phy"
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include: [phy.yaml, ethernet-controller.yaml]
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properties:
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reg:
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required: true
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description: PHY address.
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multi-gigabit-support:
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type: boolean
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description: It Enable 2.5Gbps multi-gigabit mode.

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