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sreeramIfxkartben
sreeramIfx
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drivers: gpio: Update GPIO driver to support XMC7200
Update GPIO driver to support XMC7200 Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
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-21
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+33
-21
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‎drivers/gpio/gpio_ifx_cat1.c

Lines changed: 33 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
* is not supported in current version of GPIO CAT1 driver.
1414
*/
1515

16-
#define DT_DRV_COMPAT infineon_cat1_gpio
16+
#define DT_DRV_COMPAT infineon_cat1_gpio
1717

1818
#include <zephyr/drivers/gpio.h>
1919
#include <zephyr/drivers/gpio/gpio_utils.h>
@@ -28,9 +28,11 @@ LOG_MODULE_REGISTER(gpio_cat1, CONFIG_GPIO_LOG_LEVEL);
2828
struct gpio_cat1_config {
2929
/* gpio_driver_config needs to be first */
3030
struct gpio_driver_config common;
31-
GPIO_PRT_Type *regs;
31+
GPIO_PRT_Type *regs;
3232
uint8_t ngpios;
33+
#if (!CONFIG_SOC_FAMILY_INFINEON_CAT1C)
3334
uint8_t intr_priority;
35+
#endif
3436
};
3537

3638
/* Data structure */
@@ -96,8 +98,7 @@ static int gpio_cat1_configure(const struct device *dev, gpio_pin_t pin, gpio_fl
9698
return 0;
9799
}
98100

99-
static int gpio_cat1_port_get_raw(const struct device *dev,
100-
uint32_t *value)
101+
static int gpio_cat1_port_get_raw(const struct device *dev, uint32_t *value)
101102
{
102103
const struct gpio_cat1_config *const cfg = dev->config;
103104
GPIO_PRT_Type *const base = cfg->regs;
@@ -107,8 +108,7 @@ static int gpio_cat1_port_get_raw(const struct device *dev,
107108
return 0;
108109
}
109110

110-
static int gpio_cat1_port_set_masked_raw(const struct device *dev,
111-
uint32_t mask, uint32_t value)
111+
static int gpio_cat1_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value)
112112
{
113113
const struct gpio_cat1_config *const cfg = dev->config;
114114
GPIO_PRT_Type *const base = cfg->regs;
@@ -118,8 +118,7 @@ static int gpio_cat1_port_set_masked_raw(const struct device *dev,
118118
return 0;
119119
}
120120

121-
static int gpio_cat1_port_set_bits_raw(const struct device *dev,
122-
uint32_t mask)
121+
static int gpio_cat1_port_set_bits_raw(const struct device *dev, uint32_t mask)
123122
{
124123
const struct gpio_cat1_config *const cfg = dev->config;
125124
GPIO_PRT_Type *const base = cfg->regs;
@@ -129,8 +128,7 @@ static int gpio_cat1_port_set_bits_raw(const struct device *dev,
129128
return 0;
130129
}
131130

132-
static int gpio_cat1_port_clear_bits_raw(const struct device *dev,
133-
uint32_t mask)
131+
static int gpio_cat1_port_clear_bits_raw(const struct device *dev, uint32_t mask)
134132
{
135133
const struct gpio_cat1_config *const cfg = dev->config;
136134
GPIO_PRT_Type *const base = cfg->regs;
@@ -140,8 +138,7 @@ static int gpio_cat1_port_clear_bits_raw(const struct device *dev,
140138
return 0;
141139
}
142140

143-
static int gpio_cat1_port_toggle_bits(const struct device *dev,
144-
uint32_t mask)
141+
static int gpio_cat1_port_toggle_bits(const struct device *dev, uint32_t mask)
145142
{
146143
const struct gpio_cat1_config *const cfg = dev->config;
147144
GPIO_PRT_Type *const base = cfg->regs;
@@ -159,6 +156,7 @@ static uint32_t gpio_cat1_get_pending_int(const struct device *dev)
159156
return GPIO_PRT_INTR_MASKED(base);
160157
}
161158

159+
#if (!(CONFIG_SOC_FAMILY_INFINEON_CAT1C && CONFIG_CPU_CORTEX_M0PLUS))
162160
static void gpio_isr_handler(const struct device *dev)
163161
{
164162
const struct gpio_cat1_config *const cfg = dev->config;
@@ -173,9 +171,8 @@ static void gpio_isr_handler(const struct device *dev)
173171
gpio_fire_callbacks(&((struct gpio_cat1_data *const)(dev)->data)->callbacks, dev,
174172
pins);
175173
}
176-
177-
178174
}
175+
#endif
179176

180177
static int gpio_cat1_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
181178
enum gpio_int_mode mode, enum gpio_int_trig trig)
@@ -213,8 +210,7 @@ static int gpio_cat1_pin_interrupt_configure(const struct device *dev, gpio_pin_
213210
return 0;
214211
}
215212

216-
static int gpio_cat1_manage_callback(const struct device *port,
217-
struct gpio_callback *callback,
213+
static int gpio_cat1_manage_callback(const struct device *port, struct gpio_callback *callback,
218214
bool set)
219215
{
220216
return gpio_manage_callback(&((struct gpio_cat1_data *const)(port)->data)->callbacks,
@@ -233,13 +229,29 @@ static DEVICE_API(gpio, gpio_cat1_api) = {
233229
.get_pending_int = gpio_cat1_get_pending_int,
234230
};
235231

232+
/* Interrupts are not currently supported on the Cat1C CM0+ */
233+
#if (CONFIG_SOC_FAMILY_INFINEON_CAT1C)
234+
#define INTR_PRIORITY(n)
235+
236+
#if (CONFIG_CPU_CORTEX_M0PLUS)
237+
#define ENABLE_INT(n)
238+
#else
239+
#define ENABLE_INT(n) ENABLE_SYS_INT(n, gpio_isr_handler);
240+
#endif
241+
242+
#else
243+
#define INTR_PRIORITY(n) .intr_priority = DT_INST_IRQ_BY_IDX(n, 0, priority),
244+
245+
#define ENABLE_INT(n) \
246+
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), gpio_isr_handler, \
247+
DEVICE_DT_INST_GET(n), 0); \
248+
irq_enable(DT_INST_IRQN(n));
249+
#endif
250+
236251
#define GPIO_CAT1_INIT_FUNC(n) \
237252
static int gpio_cat1##n##_init(const struct device *dev) \
238253
{ \
239-
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), gpio_isr_handler, \
240-
DEVICE_DT_INST_GET(n), 0); \
241-
irq_enable(DT_INST_IRQN(n)); \
242-
\
254+
ENABLE_INT(n) \
243255
return 0; \
244256
}
245257

@@ -250,7 +262,7 @@ static DEVICE_API(gpio, gpio_cat1_api) = {
250262
{ \
251263
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
252264
}, \
253-
.intr_priority = DT_INST_IRQ_BY_IDX(n, 0, priority), \
265+
INTR_PRIORITY(n) \
254266
.ngpios = DT_INST_PROP(n, ngpios), \
255267
.regs = (GPIO_PRT_Type *)DT_INST_REG_ADDR(n), \
256268
}; \

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