boards: avnet: add zub1cg_r5 board definition

Add board definition for the Avnet ZUBoarcd 1CG development board. This
board is based on the Zynq Ultrascale+ MPSoC. As with other boards based
on this platform, currently only the first R5 core is supported.

Signed-off-by: Michael Estes <michael.estes@byteserv.io>

Author: singular0770

boards/avnet/zub1cg_r5/Kconfig.defconfig

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+# Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_ZUB1CG_R5
+
+config BUILD_OUTPUT_BIN
+	default y
+
+if USERSPACE
+
+config COMPILER_ISA_THUMB2
+	default n
+
+endif
+
+endif # BOARD_ZUB1CG_R5

boards/avnet/zub1cg_r5/Kconfig.zub1cg_r5

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+# Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ZUB1CG_R5
+	select SOC_XILINX_ZYNQMP_RPU

boards/avnet/zub1cg_r5/board.cmake

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+# Copyright The Zephyr Project Contributors
+#
+# SPDX-License-Identifier: Apache-2.0
+include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake)

boards/avnet/zub1cg_r5/board.yml

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+board:
+  name: zub1cg_r5
+  full_name: ZUBoard 1CG Development Board RPU Cortex-R5
+  vendor: avnet
+  socs:
+  - name: zynqmp_rpu

boards/avnet/zub1cg_r5/doc/index.rst

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+.. zephyr:board:: zub1cg_r5
+
+Overview
+********
+This configuration provides support for the real-time processing unit (RPU) on the Avnet
+ZUBoard 1CG development board. It can operate as follows:
+
+* Two independent R5 cores with their own TCMs (tightly coupled memories)
+* Or, as a single dual lock step unit with double the TCM size.
+
+This processing unit is based on an ARM Cortex-R5 CPU, it also enables the following devices:
+
+* ARM PL-390 Generic Interrupt Controller
+* Xilinx Zynq TTC (Cadence TTC)
+* Xilinx Zynq UART
+* Xilinx Zynq I2C (Cadence I2C)
+
+Hardware
+********
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Devices
+========
+System Timer
+------------
+
+This board configuration uses a system timer tick frequency of 1000 Hz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+on-chip UART1.
+
+Memories
+--------
+
+Flash, DDR and OCM memory regions are defined in the DTS file.
+Vectors are placed in the ATCM region, while all other code plus
+data of the application will be loaded in the sram1 region,
+which points to the DDR memory. The sram1 region is defined to
+match the Petalinux rproc_0_reserved region so the Zephyr application
+can be launched from Petalinux using Remoteproc. The ocm0 memory
+area is currently available for usage, although nothing is placed
+there by default.
+
+Known Problems or Limitations
+==============================
+
+The following platform features are unsupported:
+
+* Dual-redundant Core Lock-step (DCLS) execution is not supported yet.
+* Only the first core of the R5 subsystem is supported.
+* Xilinx Zynq TTC driver does not support tickless mode operation.
+* The Cortex-R5 and the Cortex-A53 shares the same UART controller, more details below.
+
+Programming and Debugging
+*************************
+
+Currently the best way to run this sample is by loading it through remoteproc
+from the APU, running Linux, to the RPU, assuming the target board has a compatible
+Linux kernel. Users can make use of Avnet's pre-built Petalinux BSP as a starting
+point to enable remoteproc support, it is based around 6.6 Xilinx maintained kernel.
+Building Petalinux is outside the scope of this document, see the `Avnet ZUBoard 1CG
+Product Page`_ for more details. 
+
+After getting the Linux image running on the target board, build a Zephyr application,
+such as the hello world sample shown below:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :host-os: unix
+   :board: zub1cg_r5
+   :goals: build
+
+Due to a hardware limitation, both Linux and Zephyr share the same UART
+controller, meaning when the Zephyr application is started it will takeover the
+console from Linux.
+
+To avoid this limitation when accessing the Linux shell, the best approach is to
+connect to the board using ``ssh`` over the network (not using the FTDI
+USB interface on the board), with the dev board and the host computer
+connected to the same network.
+
+Alternatively, it is possible to use the other PS UART controller for either Linux
+or Zephyr, but it must be enabled in Vivado and routed via MIO/EMIO to accessible
+pins on the board.
+
+Assuming you are using the default ``petalinux`` user from the Xilinx
+reference image , open a terminal on the host machine and ssh into the
+development board with the board's IP address (found via ``ifconfig``):
+
+.. code-block:: console
+
+        $ ssh petalinux@<board-ip-address>
+
+The initial password should be ``petalinux``. On another terminal deploy
+the Zephyr application ``.elf`` file using utility like the ``scp`` or ``rsync``,
+for example:
+
+.. code-block:: console
+
+        $ scp /path/to/zephyr_app_elf_file  petalinux@<board-ip-address>:/home/petalinux
+
+After that move the file to ``/lib/firmware`` directory, then you be able to start the firmware
+on the desired RPU via remoteproc with:
+
+.. code-block:: console
+
+        $ sudo -i # You need to operate the remoteproc as root
+        $ echo zephyr.elf > /sys/class/remoteproc/remoteproc0/firmware
+        $ echo start > /sys/class/remoteproc/remoteproc0/state
+
+With another terminal connected to UART1 on the host machine
+(available via one of the tty ports with the on-board FTDI chip),
+you should see the Zephyr application running:
+
+.. code-block:: console
+
+        *** Booting Zephyr OS build v4.1.0-5065-gc3ec37aa2e47 ***
+        Hello World! zub1cg_r5/zynqmp_rpu
+
+It is also possible to program and debug this program via AMD's Vitis development platform.
+Create a new platform project based on your hardware XSA file (from Vivado), import a new
+empty application template, and in the debug configuration point the application to the
+zephyr.elf binary.
+
+References
+**********
+
+.. target-notes::
+
+.. _Avnet ZUBoard 1CG Product Page:
+    https://www.avnet.com/americas/products/avnet-boards/avnet-board-families/zuboard-1cg/

boards/avnet/zub1cg_r5/doc/zub1cg.webp

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+# Copyright (c) 2024 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+proc load_image args  {
+	set elf_file [lindex $args 0]
+	set fsblelf_file [lindex $args 1]
+	connect -url 127.0.0.1:3121
+	after 2000
+	targets -set -nocase -filter {name =~ "*R5*#0"}
+	rst -proc
+	dow $fsblelf_file
+	after 1000
+	con
+	after 1000
+	stop
+	targets -set -nocase -filter {name =~ "*R5*#0"}
+	after 2000
+	dow $elf_file
+	con
+	exit
+}
+
+load_image {*}$argv

boards/avnet/zub1cg_r5/support/xsdb.cfg

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+/*
+ * Copyright The Zephyr Project Contributors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <arm/xilinx/zynqmp_rpu.dtsi>
+#include <freq.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	model = "ZUBoard 1CG Cortex-R5";
+	compatible = "xlnx,zynqmp-r5";
+
+	chosen {
+		zephyr,sram = &sram1;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,ocm = &ocm;
+	};
+
+	aliases {
+		led0 = &red_led_0;
+		sw0 = &mio_push_btn;
+		eeprom-0 = &eeprom0;
+	};
+
+	leds: leds{
+		compatible = "gpio-leds";
+
+		red_led_0: d6 {
+			gpios = <&psgpio_bank1 7 GPIO_ACTIVE_HIGH>;
+			label = "D6";
+		};
+
+		red_led_1: d7 {
+			gpios = <&psgpio_bank0 25 GPIO_ACTIVE_HIGH>;
+			label = "D7";
+		};
+
+		red_led_2: d8 {
+			gpios = <&psgpio_bank0 24 GPIO_ACTIVE_HIGH>;
+			label = "D8";
+		};
+
+		red_led_3: d9 {
+			gpios = <&psgpio_bank0 7 GPIO_ACTIVE_HIGH>;
+			label = "D9";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		mio_push_btn: mio_push_btn {
+			gpios = <&psgpio_bank1 6 GPIO_ACTIVE_LOW>;
+			label = "MIO Push Button";
+		};
+
+		user_switch_1: sw1 {
+			gpios = <&psgpio_bank1 18 GPIO_ACTIVE_HIGH>;
+			label = "User Switch 1";
+		};
+
+		user_switch_2: sw2 {
+			gpios = <&psgpio_bank1 14 GPIO_ACTIVE_HIGH>;
+			label = "User Switch 2";
+		};
+
+		user_switch_3: sw3 {
+			gpios = <&psgpio_bank1 13 GPIO_ACTIVE_HIGH>;
+			label = "User Switch 3";
+		};
+
+		user_switch_4: sw4 {
+			gpios = <&psgpio_bank1 5 GPIO_ACTIVE_HIGH>;
+			label = "User Switch 4";
+		};
+	};
+
+	i2c_ref_clk: i2c_ref_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <100000000>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		/* rproc_0_reserved in Petalinux zynqmp_openamp.dtsi */
+		sram1: memory@3ed00000 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			reg = <0x3ed00000 DT_SIZE_K(256)>;
+			zephyr,memory-region = "SRAM1";
+			zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+		};
+	};
+};
+
+&ttc0 {
+	status = "okay";
+	clock-frequency = <100000000>;
+};
+
+&psgpio {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	clocks = <&i2c_ref_clk>;
+	clock-frequency = <400000>;
+
+	eeprom0: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		size = <256>;
+		pagesize = <16>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+
+	mac_eeprom: mac-eeprom@58 {
+		compatible = "atmel,at24mac402";
+		reg = <0x58>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mac_address: mac-address@9a {
+			reg = <0x9a 0x06>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <DT_FREQ_M(100)>;
+};

boards/avnet/zub1cg_r5/zub1cg_r5.dts

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+CONFIG_XIP=n
+
+CONFIG_SERIAL=y
+
+CONFIG_GPIO=y
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_UART_XLNX_PS=y
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+CONFIG_ARM_MPU=y
+
+CONFIG_ROMSTART_RELOCATION_ROM=y