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FRASTMkartben
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drivers: clock control of stm32f4 serie w/o clk 48M on PLL I2S
Some stm32f4, like the sm32f411 mcu have clk 48M on the main PLL output q Some stm32f4, like the sm32f412 mcu have clk 48M on the PLL I2S output q This PR is for selecting the right one Signed-off-by: Francois Ramu <francois.ramu@st.com>
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drivers/clock_control/clock_stm32f2_f4_f7.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -157,7 +157,8 @@ void config_plli2s(void)
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STM32_PLLI2S_N_MULTIPLIER,
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plli2sr(STM32_PLLI2S_R_DIVISOR));
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#if STM32_PLLI2S_Q_ENABLED && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
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#if STM32_PLLI2S_Q_ENABLED && \
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(defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ))
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/* There is a Q divider on the PLLI2S to configure the PLL48CK */
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LL_RCC_PLLI2S_ConfigDomain_48M(get_pll_source(),
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plli2sm(STM32_PLLI2S_M_DIVISOR),

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