arch: common: semihost: update RISC-V semihosting spec link

moonlight83340 · danieldegrasse · commit 2fc1dd54af7e · 2025-07-01T10:15:32.000-05:00
Replace dead link in include/zephyr/arch/common/semihost.h.

Signed-off-by: Gaetan Perrot &lt;gaetan.perrot@spacecubics.com&gt;
diff --git a/include/zephyr/arch/common/semihost.h b/include/zephyr/arch/common/semihost.h
@@ -8,7 +8,7 @@
  * https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst
  *
  * RISC-V semihosting also follows these conventions:
- * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
+ * https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc
  */
 
 /**

Original file line number	Diff line number	Diff line change
`@@ -8,7 +8,7 @@`
`8`	`8`	`* https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst`
`9`	`9`	`*`
`10`	`10`	`* RISC-V semihosting also follows these conventions:`
`11`		`- * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc`
	`11`	`+ * https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc`
`12`	`12`	`*/`
`13`	`13`
`14`	`14`	`/**`