soc: nordic: nrf54h: transition from gpd to zephyr pinctrl and pds

Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.

The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>

Author: bjarki-andreasen

drivers/can/can_nrf.c

@@ -17,10 +17,6 @@
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/irq.h>
 
-#ifdef CONFIG_SOC_NRF54H20_GPD
-#include <nrf/gpd.h>
-#endif
-
 /* nRF CAN wrapper offsets */
 #define CAN_TASKS_START	  offsetof(NRF_CAN_Type, TASKS_START)
 #define CAN_EVENTS_CORE_0 offsetof(NRF_CAN_Type, EVENTS_CORE[0])
@@ -187,13 +183,6 @@ static int can_nrf_init(const struct device *dev)
 	sys_write32(CAN_INTEN_CORE0_Msk | CAN_INTEN_CORE1_Msk, config->wrapper + CAN_INTEN);
 	sys_write32(1U, config->wrapper + CAN_TASKS_START);
 
-#ifdef CONFIG_SOC_NRF54H20_GPD
-	ret = nrf_gpd_retain_pins_set(config->pcfg, false);
-	if (ret < 0) {
-		return ret;
-	}
-#endif
-
 	config->irq_configure();
 
 	ret = can_mcan_configure_mram(dev, config->mrba, config->mram);

drivers/counter/counter_nrfx_timer.c

@@ -35,23 +35,9 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL);
 #define MAYBE_CONST_CONFIG const
 #endif
 
-#ifdef CONFIG_SOC_NRF54H20_GPD
-#include <nrf/gpd.h>
-
-#define NRF_CLOCKS_INSTANCE_IS_FAST(node)						\
-	COND_CODE_1(DT_NODE_HAS_PROP(node, power_domains),				\
-		    (IS_EQ(DT_PHA(node, power_domains, id), NRF_GPD_FAST_ACTIVE1)),	\
-		    (0))
-
-/* Macro must resolve to literal 0 or 1 */
-#define INSTANCE_IS_FAST(idx) NRF_CLOCKS_INSTANCE_IS_FAST(DT_DRV_INST(idx))
-
-#define INSTANCE_IS_FAST_OR(idx) INSTANCE_IS_FAST(idx) ||
-
-#if (DT_INST_FOREACH_STATUS_OKAY(INSTANCE_IS_FAST_OR) 0)
+#if NRF_DT_INST_ANY_IS_FAST
 #define COUNTER_ANY_FAST 1
 #endif
-#endif
 
 struct counter_nrfx_data {
 	counter_top_callback_t top_cb;
@@ -474,13 +460,13 @@ static DEVICE_API(counter, counter_nrfx_driver_api) = {
  * which is using nrfs (IPC) are initialized later.
  */
 #define TIMER_INIT_LEVEL(idx) \
-	COND_CODE_1(INSTANCE_IS_FAST(idx), (POST_KERNEL), (PRE_KERNEL_1))
+	COND_CODE_1(NRF_DT_INST_IS_FAST(idx), (POST_KERNEL), (PRE_KERNEL_1))
 
 /* Get initialization priority of an instance. Instances that requires clock control
  * which is using nrfs (IPC) are initialized later.
  */
 #define TIMER_INIT_PRIO(idx)								\
-	COND_CODE_1(INSTANCE_IS_FAST(idx),						\
+	COND_CODE_1(NRF_DT_INST_IS_FAST(idx),						\
 		    (UTIL_INC(CONFIG_CLOCK_CONTROL_NRF_HSFLL_GLOBAL_INIT_PRIORITY)),	\
 		    (CONFIG_COUNTER_INIT_PRIORITY))
 
@@ -536,7 +522,7 @@ static DEVICE_API(counter, counter_nrfx_driver_api) = {
 		},										\
 		.ch_data = counter##idx##_ch_data,						\
 		.timer = (NRF_TIMER_Type *)DT_INST_REG_ADDR(idx),				\
-		IF_ENABLED(INSTANCE_IS_FAST(idx),						\
+		IF_ENABLED(NRF_DT_INST_IS_FAST(idx),						\
 			(.clk_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_DRV_INST(idx))),		\
 			 .clk_spec = {								\
 				.frequency = NRF_PERIPH_GET_FREQUENCY(DT_DRV_INST(idx)),	\

drivers/gpio/gpio_nrfx.c

@@ -16,8 +16,10 @@
 
 #include <zephyr/drivers/gpio/gpio_utils.h>
 
-#ifdef CONFIG_SOC_NRF54H20_GPD
-#include <nrf/gpd.h>
+#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_gpio_pad_group)
+#define NRF_GPIO_HAS_PAD_GROUP 1
+#else
+#define NRF_GPIO_HAS_PAD_GROUP 0
 #endif
 
 struct gpio_nrfx_data {
@@ -33,8 +35,8 @@ struct gpio_nrfx_cfg {
 	uint32_t edge_sense;
 	uint8_t port_num;
 	nrfx_gpiote_t gpiote;
-#ifdef CONFIG_SOC_NRF54H20_GPD
-	uint8_t pad_pd;
+#if NRF_GPIO_HAS_PAD_GROUP
+	const struct device *pad_group;
 #endif
 };
 
@@ -64,30 +66,6 @@ static nrf_gpio_pin_pull_t get_pull(gpio_flags_t flags)
 	return NRF_GPIO_PIN_NOPULL;
 }
 
-static void gpio_nrfx_gpd_retain_set(const struct device *port, uint32_t mask)
-{
-#ifdef CONFIG_SOC_NRF54H20_GPD
-	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
-
-	nrf_gpio_port_retain_enable(cfg->port, mask);
-#else
-	ARG_UNUSED(port);
-	ARG_UNUSED(mask);
-#endif
-}
-
-static void gpio_nrfx_gpd_retain_clear(const struct device *port, uint32_t mask)
-{
-#ifdef CONFIG_SOC_NRF54H20_GPD
-	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
-
-	nrf_gpio_port_retain_disable(cfg->port, mask);
-#else
-	ARG_UNUSED(port);
-	ARG_UNUSED(mask);
-#endif
-}
-
 static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin,
 				   gpio_flags_t flags)
 {
@@ -134,8 +112,6 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin,
 		return ret;
 	}
 
-	gpio_nrfx_gpd_retain_clear(port, BIT(pin));
-
 	if (flags & GPIO_OUTPUT_INIT_HIGH) {
 		nrf_gpio_port_out_set(cfg->port, BIT(pin));
 	} else if (flags & GPIO_OUTPUT_INIT_LOW) {
@@ -216,7 +192,6 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin,
 	}
 
 end:
-	gpio_nrfx_gpd_retain_set(port, BIT(pin));
 	return pm_device_runtime_put(port);
 }
 
@@ -317,10 +292,8 @@ static int gpio_nrfx_port_set_masked_raw(const struct device *port,
 		return ret;
 	}
 
-	gpio_nrfx_gpd_retain_clear(port, mask);
 	nrf_gpio_port_out_set(reg, set_mask);
 	nrf_gpio_port_out_clear(reg, clear_mask);
-	gpio_nrfx_gpd_retain_set(port, mask);
 	return pm_device_runtime_put(port);
 }
 
@@ -335,9 +308,7 @@ static int gpio_nrfx_port_set_bits_raw(const struct device *port,
 		return ret;
 	}
 
-	gpio_nrfx_gpd_retain_clear(port, mask);
 	nrf_gpio_port_out_set(reg, mask);
-	gpio_nrfx_gpd_retain_set(port, mask);
 	return pm_device_runtime_put(port);
 }
 
@@ -352,9 +323,7 @@ static int gpio_nrfx_port_clear_bits_raw(const struct device *port,
 		return ret;
 	}
 
-	gpio_nrfx_gpd_retain_clear(port, mask);
 	nrf_gpio_port_out_clear(reg, mask);
-	gpio_nrfx_gpd_retain_set(port, mask);
 	return pm_device_runtime_put(port);
 }
 
@@ -372,10 +341,8 @@ static int gpio_nrfx_port_toggle_bits(const struct device *port,
 		return ret;
 	}
 
-	gpio_nrfx_gpd_retain_clear(port, mask);
 	nrf_gpio_port_out_set(reg, set_mask);
 	nrf_gpio_port_out_clear(reg, clear_mask);
-	gpio_nrfx_gpd_retain_set(port, mask);
 	return pm_device_runtime_put(port);
 }
 
@@ -546,14 +513,10 @@ static void nrfx_gpio_handler(nrfx_gpiote_pin_t abs_pin,
 
 static int gpio_nrfx_pm_suspend(const struct device *port)
 {
-#ifdef CONFIG_SOC_NRF54H20_GPD
+#if NRF_GPIO_HAS_PAD_GROUP
 	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
 
-	if (cfg->pad_pd != NRF_GPD_FAST_ACTIVE1) {
-		return 0;
-	}
-
-	return nrf_gpd_release(NRF_GPD_FAST_ACTIVE1);
+	return pm_device_runtime_put(cfg->pad_group);
 #else
 	ARG_UNUSED(port);
 	return 0;
@@ -562,14 +525,10 @@ static int gpio_nrfx_pm_suspend(const struct device *port)
 
 static int gpio_nrfx_pm_resume(const struct device *port)
 {
-#ifdef CONFIG_SOC_NRF54H20_GPD
+#if NRF_GPIO_HAS_PAD_GROUP
 	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
 
-	if (cfg->pad_pd != NRF_GPD_FAST_ACTIVE1) {
-		return 0;
-	}
-
-	return nrf_gpd_request(NRF_GPD_FAST_ACTIVE1);
+	return pm_device_runtime_get(cfg->pad_group);
 #else
 	ARG_UNUSED(port);
 	return 0;
@@ -660,12 +619,11 @@ static DEVICE_API(gpio, gpio_nrfx_drv_api_funcs) = {
 			"Please enable GPIOTE instance for used GPIO port!")), \
 		())
 
-#ifdef CONFIG_SOC_NRF54H20_GPD
-#define PAD_PD(inst) \
-	.pad_pd = DT_INST_PHA_BY_NAME_OR(inst, power_domains, pad, id,	       \
-					 NRF_GPD_SLOW_MAIN),
+#if NRF_GPIO_HAS_PAD_GROUP
+#define GPIO_NRF_PAD_GROUP_INIT(id) \
+	.pad_group = DEVICE_DT_GET(DT_INST_CHILD(id, pad_group)),
 #else
-#define PAD_PD(inst)
+#define GPIO_NRF_PAD_GROUP_INIT(id)
 #endif
 
 #define GPIO_NRF_DEVICE(id)						\
@@ -679,7 +637,7 @@ static DEVICE_API(gpio, gpio_nrfx_drv_api_funcs) = {
 		.port_num = DT_INST_PROP(id, port),			\
 		.edge_sense = DT_INST_PROP_OR(id, sense_edge_mask, 0),	\
 		.gpiote = GPIOTE_INSTANCE(id),				\
-		PAD_PD(id)						\
+		GPIO_NRF_PAD_GROUP_INIT(id)				\
 	};								\
 									\
 	static struct gpio_nrfx_data gpio_nrfx_p##id##_data;		\