@@ -67,9 +67,11 @@ LOG_MODULE_REGISTER(usb_dc_stm32);
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static const struct stm32_pclken pclken [] = STM32_DT_INST_CLOCKS (0 );
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+ #if !DT_HAS_COMPAT_STATUS_OKAY (st_stm32n6_otghs )
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PINCTRL_DT_INST_DEFINE (0 );
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static const struct pinctrl_dev_config * usb_pcfg =
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PINCTRL_DT_INST_DEV_CONFIG_GET (0 );
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+ #endif
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#define USB_OTG_HS_EMB_PHYC (DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) && \
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DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
@@ -339,6 +341,14 @@ static int usb_dc_stm32_phy_specific_clock_enable(const struct device *const clk
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* with LL_PWR_EnableVDDUSB function (higher case)
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*/
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LL_PWR_EnableVDDUSB ();
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+ #elif DT_HAS_COMPAT_STATUS_OKAY (st_stm32n6_otghs )
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+ /* Enable Vdd USB voltage monitoring */
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+ LL_PWR_EnableVddUSBMonitoring ();
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+ while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY )) {
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+ /* Wait for VDD33USB ready */
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+ }
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+ /* Enable VDDUSB */
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+ LL_PWR_EnableVddUSB ();
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#endif
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if (DT_INST_NUM_CLOCKS (0 ) > 1 ) {
@@ -417,13 +427,15 @@ static int usb_dc_stm32_clock_enable(void)
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/* Both OTG HS and USBPHY sleep clock MUST be disabled here at the same time */
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LL_AHB2_GRP1_DisableClockStopSleep (LL_AHB2_GRP1_PERIPH_OTG_HS ||
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LL_AHB2_GRP1_PERIPH_USBPHY );
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- #else
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+ #elif ! DT_HAS_COMPAT_STATUS_OKAY ( st_stm32n6_otghs )
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LL_AHB1_GRP1_DisableClockLowPower (LL_AHB1_GRP1_PERIPH_OTGHSULPI );
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#endif
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#if USB_OTG_HS_EMB_PHYC
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+ #if !DT_HAS_COMPAT_STATUS_OKAY (st_stm32n6_otghs )
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LL_APB2_GRP1_EnableClock (LL_APB2_GRP1_PERIPH_OTGPHYC );
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#endif
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+ #endif
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#endif /* USB_OTG_HS_ULPI_PHY */
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return 0 ;
@@ -511,12 +523,14 @@ static int usb_dc_stm32_init(void)
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}
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#endif
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+ #if !DT_HAS_COMPAT_STATUS_OKAY (st_stm32n6_otghs )
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LOG_DBG ("Pinctrl signals configuration" );
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ret = pinctrl_apply_state (usb_pcfg , PINCTRL_STATE_DEFAULT );
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if (ret < 0 ) {
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LOG_ERR ("USB pinctrl setup failed (%d)" , ret );
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return ret ;
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}
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+ #endif
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LOG_DBG ("HAL_PCD_Init" );
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status = HAL_PCD_Init (& usb_dc_stm32_state .pcd );
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