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LucasTamborkartben
LucasTambor
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kartben
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drivers: uart: espressif: Add LP UART driver
Add LP UART driver for LP Core Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
1 parent 0b79b47 commit 232e2c5

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‎boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi renamed to ‎boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore-pinctrl.dtsi

File renamed without changes.

‎boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts

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@@ -7,7 +7,7 @@
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/dts-v1/;
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#include <espressif/esp32c6/esp32c6_wroom_n8.dtsi>
10-
#include "esp32c6_devkitc-pinctrl.dtsi"
10+
#include "esp32c6_devkitc_hpcore-pinctrl.dtsi"
1111
#include <zephyr/dt-bindings/input/input-event-codes.h>
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#include <espressif/partitions_0x0_default.dtsi>
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‎boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.dts

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@@ -15,5 +15,12 @@
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chosen {
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zephyr,sram = &sramlp;
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zephyr,code-partition = &slot0_lpcore_partition;
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zephyr,console = &lp_uart;
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zephyr,shell-uart = &lp_uart;
1820
};
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};
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&lp_uart {
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status = "okay";
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current-speed = <115200>;
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};

‎boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.yaml

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@@ -6,6 +6,8 @@ toolchain:
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- zephyr
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supported:
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- cpu
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- uart
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- serial
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testing:
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only_tags:
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- introduction

‎boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig

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@@ -9,7 +9,11 @@ CONFIG_THREAD_CUSTOM_DATA=n
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CONFIG_BOOT_BANNER=n
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# Console
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CONFIG_SERIAL=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_PRINTK=n
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CONFIG_CBPRINTF_NANO=y
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# Build
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CONFIG_SIZE_OPTIMIZATIONS=y

‎drivers/serial/CMakeLists.txt

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@@ -15,6 +15,7 @@ zephyr_library_sources_ifdef(CONFIG_USB_CDC_ACM ${ZEPHYR_BASE}/misc/empty_file.c
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# zephyr-keep-sorted-start
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zephyr_library_sources_ifdef(CONFIG_LEUART_GECKO leuart_gecko.c)
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zephyr_library_sources_ifdef(CONFIG_LPUART_ESP32 lpuart_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_SERIAL_ESP32_USB serial_esp32_usb.c)
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zephyr_library_sources_ifdef(CONFIG_UART_ALTERA uart_altera.c)
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zephyr_library_sources_ifdef(CONFIG_UART_ALTERA_JTAG uart_altera_jtag.c)

‎drivers/serial/Kconfig.esp32

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@@ -43,3 +43,11 @@ config UART_ESP32_RX_FIFO_THRESH
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range 1 127
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help
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Configure the RX FIFO threshold for ESP32 UART driver.
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config LPUART_ESP32
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bool "ESP32 LP UART driver"
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default y
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depends on DT_HAS_ESPRESSIF_ESP32_LPUART_ENABLED
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select SERIAL_HAS_DRIVER
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help
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Enable the ESP32 LP UART.

‎drivers/serial/lpuart_esp32.c

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@@ -0,0 +1,204 @@
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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_lpuart
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#include <zephyr/drivers/uart.h>
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#include <zephyr/dt-bindings/clock/esp32c6_clock.h>
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#include <hal/uart_hal.h>
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#if defined(CONFIG_SOC_ESP32C6_HPCORE)
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#include <hal/uart_ll.h>
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#include <hal/clk_tree_ll.h>
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#include <hal/clk_tree_hal.h>
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#include <hal/rtc_io_hal.h>
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#include <soc/uart_pins.h>
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#include <soc/rtc_io_periph.h>
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#include <esp_private/esp_clk_tree_common.h>
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#include <ulp_lp_core_uart.h>
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#endif
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#define ESP_LP_UART_TX_IDLE_NUM_DEFAULT (0U)
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struct lp_uart_esp32_data {
27+
uart_hal_context_t hal;
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};
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struct lp_uart_esp32_config {
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uint8_t tx_io_num;
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uint8_t rx_io_num;
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uint8_t rts_io_num;
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uint8_t cts_io_num;
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int baud_rate;
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uint8_t data_bits;
37+
uint8_t parity;
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uint8_t stop_bits;
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uint8_t flow_ctrl;
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uint8_t rx_flow_ctrl_thresh;
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uint8_t lp_uart_source_clk;
42+
};
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static int lp_uart_esp32_poll_in(const struct device *dev, unsigned char *p_char)
45+
{
46+
struct lp_uart_esp32_data *data = dev->data;
47+
int inout_rd_len = 1;
48+
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if (uart_hal_get_rxfifo_len(&data->hal) == 0) {
50+
return -1;
51+
}
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uart_hal_read_rxfifo(&data->hal, p_char, &inout_rd_len);
54+
55+
return 0;
56+
}
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static void lp_uart_esp32_poll_out(const struct device *dev, unsigned char c)
59+
{
60+
struct lp_uart_esp32_data *data = dev->data;
61+
int tx_len = 0;
62+
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/* Wait for space in FIFO */
64+
while (uart_hal_get_txfifo_len(&data->hal) == 0) {
65+
; /* Wait */
66+
}
67+
68+
uart_hal_write_txfifo(&data->hal, (const void *)&c, 1, &tx_len);
69+
}
70+
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#if defined(CONFIG_SOC_ESP32C6_HPCORE)
72+
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static int lp_uart_esp32_param_config(const struct device *dev)
74+
{
75+
const struct lp_uart_esp32_config *const cfg = dev->config;
76+
struct lp_uart_esp32_data *data = dev->data;
77+
uint32_t sclk_freq = 0;
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79+
if ((cfg->rx_flow_ctrl_thresh > SOC_LP_UART_FIFO_LEN) ||
80+
(cfg->flow_ctrl > UART_CFG_FLOW_CTRL_RTS_CTS) ||
81+
(cfg->data_bits > UART_CFG_DATA_BITS_8)) {
82+
return -EINVAL;
83+
}
84+
85+
/* Get LP UART source clock frequency */
86+
switch (clk_ll_rtc_fast_get_src()) {
87+
case SOC_RTC_FAST_CLK_SRC_XTAL_DIV:
88+
#if CONFIG_SOC_SERIES_ESP32 || CONFIG_SOC_SERIES_ESP32S2 /* SOC_RTC_FAST_CLK_SRC_XTAL_D4 */
89+
sclk_freq = clk_hal_xtal_get_freq_mhz() * MHZ(1) >> 2;
90+
#else /* SOC_RTC_FAST_CLK_SRC_XTAL_D2 */
91+
sclk_freq = clk_hal_xtal_get_freq_mhz() * MHZ(1) >> 1;
92+
#endif
93+
break;
94+
case SOC_RTC_FAST_CLK_SRC_RC_FAST:
95+
sclk_freq =
96+
esp_clk_tree_rc_fast_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED) /
97+
clk_ll_rc_fast_get_divider();
98+
break;
99+
#if SOC_CLK_LP_FAST_SUPPORT_LP_PLL
100+
case SOC_RTC_FAST_CLK_SRC_LP_PLL:
101+
sclk_freq = clk_ll_lp_pll_get_freq_mhz() * MHZ(1);
102+
break;
103+
#endif
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default:
105+
return -EINVAL;
106+
}
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108+
lp_uart_ll_enable_bus_clock(0, true);
109+
lp_uart_ll_set_source_clk(data->hal.dev, cfg->lp_uart_source_clk);
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lp_uart_ll_sclk_enable(0);
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/* Initialize LP UART HAL with default parameters */
113+
uart_hal_init(&data->hal, LP_UART_NUM_0);
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/* Set protocol parameters from the configuration */
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lp_uart_ll_set_baudrate(data->hal.dev, cfg->baud_rate, sclk_freq);
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uart_hal_set_parity(&data->hal, cfg->parity);
118+
uart_hal_set_data_bit_num(&data->hal, cfg->data_bits);
119+
uart_hal_set_stop_bits(&data->hal, cfg->stop_bits);
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uart_hal_set_tx_idle_num(&data->hal, ESP_LP_UART_TX_IDLE_NUM_DEFAULT);
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uart_hal_set_hw_flow_ctrl(&data->hal, cfg->flow_ctrl, cfg->rx_flow_ctrl_thresh);
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123+
/* Reset Tx/Rx FIFOs */
124+
uart_hal_rxfifo_rst(&data->hal);
125+
uart_hal_txfifo_rst(&data->hal);
126+
127+
return 0;
128+
}
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130+
static void lp_uart_esp32_config_io(int pin, int direction, int func)
131+
{
132+
int rtc_io_num = rtc_io_num_map[pin];
133+
134+
rtcio_hal_function_select(rtc_io_num, RTCIO_FUNC_RTC);
135+
rtcio_hal_set_direction(rtc_io_num, direction);
136+
rtcio_hal_iomux_func_sel(rtc_io_num, func);
137+
}
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139+
static void lp_uart_esp32_set_pin(const struct device *dev)
140+
{
141+
const struct lp_uart_esp32_config *const cfg = dev->config;
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/* Configure Tx Pin */
144+
lp_uart_esp32_config_io(cfg->tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, LP_U0TXD_MUX_FUNC);
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/* Configure Rx Pin */
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lp_uart_esp32_config_io(cfg->rx_io_num, RTC_GPIO_MODE_INPUT_ONLY, LP_U0RXD_GPIO_NUM);
148+
149+
/* Configure RTS Pin */
150+
lp_uart_esp32_config_io(cfg->rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, LP_U0RTS_MUX_FUNC);
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152+
/* Configure CTS Pin */
153+
lp_uart_esp32_config_io(cfg->cts_io_num, RTC_GPIO_MODE_INPUT_ONLY, LP_U0CTS_MUX_FUNC);
154+
}
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156+
static int lp_uart_esp32_init(const struct device *dev)
157+
{
158+
int ret = 0;
159+
160+
ret = lp_uart_esp32_param_config(dev);
161+
if (ret != 0) {
162+
return -EINVAL;
163+
}
164+
165+
/* Configure LP UART IO pins */
166+
lp_uart_esp32_set_pin(dev);
167+
return 0;
168+
}
169+
170+
#endif /* CONFIG_SOC_ESP32C6_HPCORE */
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172+
static DEVICE_API(uart, lp_uart_esp32_api) = {
173+
.poll_in = lp_uart_esp32_poll_in,
174+
.poll_out = lp_uart_esp32_poll_out,
175+
};
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static struct lp_uart_esp32_data lp_uart_esp32_data = {
178+
.hal = {
179+
.dev = (uart_dev_t *)DT_REG_ADDR(DT_NODELABEL(lp_uart)),
180+
},
181+
};
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static const struct lp_uart_esp32_config lp_uart_esp32_cfg = {
184+
.tx_io_num = DT_PROP(DT_NODELABEL(lp_uart), tx_pin),
185+
.rx_io_num = DT_PROP(DT_NODELABEL(lp_uart), rx_pin),
186+
.rts_io_num = DT_PROP(DT_NODELABEL(lp_uart), rts_pin),
187+
.cts_io_num = DT_PROP(DT_NODELABEL(lp_uart), cts_pin),
188+
.baud_rate = DT_PROP(DT_NODELABEL(lp_uart), current_speed),
189+
.data_bits = DT_PROP_OR(DT_NODELABEL(lp_uart), data_bits, UART_CFG_DATA_BITS_8),
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.parity = DT_ENUM_IDX(DT_NODELABEL(lp_uart), parity),
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.stop_bits = DT_PROP_OR(DT_NODELABEL(lp_uart), stop_bits, UART_CFG_STOP_BITS_1),
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.flow_ctrl = DT_PROP_OR(DT_NODELABEL(lp_uart), flow_ctrl, UART_CFG_FLOW_CTRL_NONE),
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.rx_flow_ctrl_thresh = 0,
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.lp_uart_source_clk = LP_UART_SCLK_DEFAULT,
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};
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#if defined(CONFIG_SOC_ESP32C6_HPCORE)
198+
#define LP_UART_ESP32_INIT_FUNC lp_uart_esp32_init
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#else
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#define LP_UART_ESP32_INIT_FUNC NULL
201+
#endif
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DEVICE_DT_DEFINE(DT_NODELABEL(lp_uart), LP_UART_ESP32_INIT_FUNC, NULL, &lp_uart_esp32_data,
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&lp_uart_esp32_cfg, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, &lp_uart_esp32_api);

‎dts/bindings/serial/espressif,esp32-lpuart.yaml

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description: ESP32 Low Power UART
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compatible: "espressif,esp32-lpuart"
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include: uart-controller.yaml
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properties:
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reg:
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required: true
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tx-pin:
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type: int
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default: 5
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enum:
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- 5
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description: In ESP32-C6, TX pin is fixed to GPIO5
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rx-pin:
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type: int
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default: 4
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enum:
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- 4
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description: In ESP32-C6, RX pin is fixed to GPIO4
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rts-pin:
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type: int
27+
default: 2
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enum:
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- 2
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description: In ESP32-C6, RTS pin is fixed to GPIO2
31+
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cts-pin:
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type: int
34+
default: 3
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enum:
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- 3
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description: In ESP32-C6, CTS pin is fixed to GPIO3
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current-speed:
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type: int

‎dts/riscv/espressif/esp32c6/esp32c6_common.dtsi

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@@ -274,6 +274,13 @@
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current-speed = <115200>;
275275
};
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lp_uart: uart@600b1400 {
278+
compatible = "espressif,esp32-lpuart";
279+
reg = <0x600b1400 DT_SIZE_K(4)>;
280+
status = "disabled";
281+
current-speed = <115200>;
282+
};
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usb_serial: uart@6000f000 {
278285
compatible = "espressif,esp32-usb-serial";
279286
reg = <0x6000F000 0x1000>;

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