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7 | 7 | #include <arm/armv8-m.dtsi>
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8 | 8 | #include <freq.h>
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9 | 9 | #include <mem.h>
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| 10 | +#include <zephyr/dt-bindings/gpio/gpio.h> |
| 11 | +#include <zephyr/dt-bindings/clock/stm32mp2_clock.h> |
10 | 12 |
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11 | 13 | / {
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12 | 14 | cpus {
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56 | 58 | <8 1>, <9 1>, <10 1>, <11 1>,
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57 | 59 | <12 1>, <13 1>, <14 1>, <15 1>;
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58 | 60 | };
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| 61 | + |
| 62 | + pinctrl: pin-controller@44240000 { |
| 63 | + compatible = "st,stm32-pinctrl"; |
| 64 | + #address-cells = <1>; |
| 65 | + #size-cells = <1>; |
| 66 | + reg = <0x44240000 0xb0000>; |
| 67 | + |
| 68 | + gpioa: gpio@44240000 { |
| 69 | + compatible = "st,stm32mp2-gpio"; |
| 70 | + gpio-controller; |
| 71 | + #gpio-cells = <2>; |
| 72 | + reg = <0x44240000 DT_SIZE_K(1)>; |
| 73 | + status = "disabled"; |
| 74 | + }; |
| 75 | + |
| 76 | + gpiob: gpio@44250000 { |
| 77 | + compatible = "st,stm32mp2-gpio"; |
| 78 | + gpio-controller; |
| 79 | + #gpio-cells = <2>; |
| 80 | + reg = <0x44250000 DT_SIZE_K(1)>; |
| 81 | + status = "disabled"; |
| 82 | + }; |
| 83 | + |
| 84 | + gpioc: gpio@44260000 { |
| 85 | + compatible = "st,stm32mp2-gpio"; |
| 86 | + gpio-controller; |
| 87 | + #gpio-cells = <2>; |
| 88 | + reg = <0x44260000 DT_SIZE_K(1)>; |
| 89 | + status = "disabled"; |
| 90 | + }; |
| 91 | + |
| 92 | + gpiod: gpio@44270000 { |
| 93 | + compatible = "st,stm32mp2-gpio"; |
| 94 | + gpio-controller; |
| 95 | + #gpio-cells = <2>; |
| 96 | + reg = <0x44270000 DT_SIZE_K(1)>; |
| 97 | + status = "disabled"; |
| 98 | + }; |
| 99 | + |
| 100 | + gpioe: gpio@44280000 { |
| 101 | + compatible = "st,stm32mp2-gpio"; |
| 102 | + gpio-controller; |
| 103 | + #gpio-cells = <2>; |
| 104 | + reg = <0x44280000 DT_SIZE_K(1)>; |
| 105 | + status = "disabled"; |
| 106 | + }; |
| 107 | + |
| 108 | + gpiof: gpio@44290000 { |
| 109 | + compatible = "st,stm32mp2-gpio"; |
| 110 | + gpio-controller; |
| 111 | + #gpio-cells = <2>; |
| 112 | + reg = <0x44290000 DT_SIZE_K(1)>; |
| 113 | + status = "disabled"; |
| 114 | + }; |
| 115 | + |
| 116 | + gpiog: gpio@442a0000 { |
| 117 | + compatible = "st,stm32mp2-gpio"; |
| 118 | + gpio-controller; |
| 119 | + #gpio-cells = <2>; |
| 120 | + reg = <0x442a0000 DT_SIZE_K(1)>; |
| 121 | + status = "disabled"; |
| 122 | + }; |
| 123 | + |
| 124 | + gpioh: gpio@442b0000 { |
| 125 | + compatible = "st,stm32mp2-gpio"; |
| 126 | + gpio-controller; |
| 127 | + #gpio-cells = <2>; |
| 128 | + reg = <0x442b0000 DT_SIZE_K(1)>; |
| 129 | + status = "disabled"; |
| 130 | + }; |
| 131 | + |
| 132 | + gpioi: gpio@442c0000 { |
| 133 | + compatible = "st,stm32mp2-gpio"; |
| 134 | + gpio-controller; |
| 135 | + #gpio-cells = <2>; |
| 136 | + reg = <0x442c0000 DT_SIZE_K(1)>; |
| 137 | + status = "disabled"; |
| 138 | + }; |
| 139 | + |
| 140 | + gpioj: gpio@442d0000 { |
| 141 | + compatible = "st,stm32mp2-gpio"; |
| 142 | + gpio-controller; |
| 143 | + #gpio-cells = <2>; |
| 144 | + reg = <0x442d0000 DT_SIZE_K(1)>; |
| 145 | + status = "disabled"; |
| 146 | + }; |
| 147 | + |
| 148 | + gpiok: gpio@442e0000 { |
| 149 | + compatible = "st,stm32mp2-gpio"; |
| 150 | + gpio-controller; |
| 151 | + #gpio-cells = <2>; |
| 152 | + reg = <0x442e0000 DT_SIZE_K(1)>; |
| 153 | + status = "disabled"; |
| 154 | + }; |
| 155 | + }; |
59 | 156 | };
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60 | 157 | };
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61 | 158 |
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