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drivers: dm8806: add new driver for davicom dm8806 phy mac
New driver for Davicom DM8806 PHY. Driver is using standar mdio API to manage the DM8806 switch controller. Register access needs the PHY addres or switch address to be one of five possible values, since DM8806 has built-in five PHY's. These values should be defined in the application .dts file. One DM8806 ethernet port must corresponds with one ethernet PHY node with two properties for ethernet port: one for PHY address and one for switch address - <reg> for register access from Internal PHY Register area and <reg-switch> for register access from Switch Per-Port Registers area. Device tree example below: example device-tree: dm8806_phy: ethernet-phy@0 { reg = <2>; reg-switch = <8>; compatible = "davicom,dm8806-phy"; status = "okay"; davicom,interface-type = "rmii"; reset-gpio = <&gpiod 2 GPIO_ACTIVE_LOW>; interrupt-gpio = <&gpioc 1 GPIO_ACTIVE_HIGH>; }; Signed-off-by: Robert Slawinski <robert.slawinski1@gmail.com>
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‎drivers/ethernet/phy/CMakeLists.txt

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@@ -2,6 +2,7 @@
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zephyr_library_sources_ifdef(CONFIG_PHY_GENERIC_MII phy_mii.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_ADIN2111 phy_adin2111.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_DM8806 phy_dm8806.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_TJA1103 phy_tja1103.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_KSZ8081 phy_microchip_ksz8081.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_TI_DP83825 phy_ti_dp83825.c)

‎drivers/ethernet/phy/Kconfig

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@@ -40,6 +40,13 @@ config PHY_ADIN2111
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help
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Enable ADIN2111 PHY driver.
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config PHY_DM8806
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bool "DM8806 PHY driver"
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default y
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depends on DT_HAS_DAVICOM_DM8806_PHY_ENABLED
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help
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Enable DM8806 PHY driver.
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config PHY_MICROCHIP_KSZ8081
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bool "Microchip KSZ8081 PHY Driver"
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default y

‎drivers/ethernet/phy/phy_dm8806.c

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/*
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* Copyright (c) 2024 Robert Slawinski <robert.slawinski1@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT davicom_dm8806_phy
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(eth_dm8806_phy, CONFIG_ETHERNET_LOG_LEVEL);
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#include <stdio.h>
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#include <sys/types.h>
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#include <zephyr/kernel.h>
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#include <zephyr/net/phy.h>
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#include <zephyr/drivers/mdio.h>
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#include <zephyr/drivers/gpio.h>
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#include "phy_dm8806_priv.h"
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struct phy_dm8806_config {
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const struct device *mdio;
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uint8_t phy_addr;
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uint8_t switch_addr;
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struct gpio_dt_spec gpio_rst;
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struct gpio_dt_spec gpio_int;
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bool mii;
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};
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struct phy_dm8806_data {
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const struct device *dev;
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struct phy_link_state state;
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struct k_sem sem;
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struct k_work_delayable monitor_work;
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phy_callback_t cb;
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void *cb_data;
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};
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static int phy_dm8806_init(const struct device *dev)
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{
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int ret;
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uint16_t val;
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const struct phy_dm8806_config *cfg = dev->config;
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ret = mdio_read(cfg->mdio, PHY_ADDRESS_18H, PORT5_MAC_CONTROL, &val);
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if (ret) {
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LOG_ERR("Failed to read PORT5_MAC_CONTROL: %i", ret);
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return ret;
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}
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/* Activate default working mode*/
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val |= (P5_50M_INT_CLK_SOURCE | P5_50M_CLK_OUT_ENABLE | P5_EN_FORCE);
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val &= (P5_SPEED_100M | P5_FULL_DUPLEX | P5_FORCE_LINK_ON);
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ret = mdio_write(cfg->mdio, PHY_ADDRESS_18H, PORT5_MAC_CONTROL, val);
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if (ret) {
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LOG_ERR("Failed to write PORT5_MAC_CONTROL, %i", ret);
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return ret;
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}
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ret = mdio_read(cfg->mdio, PHY_ADDRESS_18H, IRQ_LED_CONTROL, &val);
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if (ret) {
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LOG_ERR("Failed to read IRQ_LED_CONTROL, %i", ret);
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return ret;
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}
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/* Activate LED blinking mode indicator mode 0. */
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val &= LED_MODE_0;
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ret = mdio_write(cfg->mdio, PHY_ADDRESS_18H, IRQ_LED_CONTROL, val);
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if (ret) {
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LOG_ERR("Failed to write IRQ_LED_CONTROL, %i", ret);
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return ret;
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}
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return 0;
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}
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static int phy_dm8806_get_link_state(const struct device *dev, struct phy_link_state *state)
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{
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int ret;
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uint16_t status;
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uint16_t data;
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const struct phy_dm8806_config *cfg = dev->config;
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/* Read data from Switch Per-Port Register. */
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ret = mdio_read(cfg->mdio, cfg->switch_addr, PORTX_SWITCH_STATUS, &data);
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if (ret) {
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LOG_ERR("Failes to read data drom DM8806 Switch Per-Port Registers area");
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return ret;
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}
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/* Extract speed and duplex status from Switch Per-Port Register: Per Port
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* Status Data Register
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*/
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status = data;
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status >>= SPEED_AND_DUPLEX_OFFSET;
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switch (status & SPEED_AND_DUPLEX_MASK) {
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case SPEED_10MBPS_HALF_DUPLEX:
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state->speed = LINK_HALF_10BASE_T;
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break;
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case SPEED_10MBPS_FULL_DUPLEX:
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state->speed = LINK_FULL_10BASE_T;
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break;
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case SPEED_100MBPS_HALF_DUPLEX:
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state->speed = LINK_HALF_100BASE_T;
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break;
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case SPEED_100MBPS_FULL_DUPLEX:
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state->speed = LINK_FULL_100BASE_T;
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break;
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}
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/* Extract link status from Switch Per-Port Register: Per Port Status Data
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* Register
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*/
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status = data;
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if (status & LINK_STATUS_MASK) {
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state->is_up = true;
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} else {
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state->is_up = false;
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}
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return ret;
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}
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static int phy_dm8806_cfg_link(const struct device *dev, enum phy_link_speed adv_speeds)
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{
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uint8_t ret;
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uint16_t data;
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uint16_t req_speed;
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const struct phy_dm8806_config *cfg = dev->config;
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req_speed = adv_speeds;
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switch (req_speed) {
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case LINK_HALF_10BASE_T:
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req_speed = MODE_10_BASET_HALF_DUPLEX;
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break;
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case LINK_FULL_10BASE_T:
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req_speed = MODE_10_BASET_FULL_DUPLEX;
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break;
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case LINK_HALF_100BASE_T:
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req_speed = MODE_100_BASET_HALF_DUPLEX;
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break;
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case LINK_FULL_100BASE_T:
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req_speed = MODE_100_BASET_FULL_DUPLEX;
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break;
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}
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/* Power down */
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ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data);
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if (ret) {
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LOG_ERR("Failes to read data drom DM8806");
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return ret;
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}
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data |= POWER_DOWN;
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ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data);
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if (ret) {
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LOG_ERR("Failed to write data to DM8806");
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return ret;
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}
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/* Turn off the auto-negotiation process. */
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ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data);
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if (ret) {
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LOG_ERR("Failed to write data to DM8806");
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return ret;
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}
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data &= ~(AUTO_NEGOTIATION);
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ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data);
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if (ret) {
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LOG_ERR("Failed to write data to DM8806");
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return ret;
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}
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/* Change the link speed. */
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ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data);
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if (ret) {
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LOG_ERR("Failed to read data from DM8806");
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return ret;
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}
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data &= ~(LINK_SPEED | DUPLEX_MODE);
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data |= req_speed;
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ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data);
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if (ret) {
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LOG_ERR("Failed to write data to DM8806");
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return ret;
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}
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/* Power up ethernet port*/
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ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data);
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if (ret) {
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LOG_ERR("Failes to read data drom DM8806");
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return ret;
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}
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data &= ~(POWER_DOWN);
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ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data);
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if (ret) {
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LOG_ERR("Failed to write data to DM8806");
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return ret;
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}
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return -ENOTSUP;
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}
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static int phy_dm8806_link_cb_set(const struct device *dev, phy_callback_t cb, void *user_data)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(cb);
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ARG_UNUSED(user_data);
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return -ENOTSUP;
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}
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static int phy_dm8806_reg_read(const struct device *dev, uint16_t phy_addr, uint16_t reg_addr,
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uint32_t *data)
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{
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int res;
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const struct phy_dm8806_config *cfg = dev->config;
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res = mdio_read(cfg->mdio, phy_addr, reg_addr, (uint16_t *)data);
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if (res) {
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LOG_ERR("Failed to read data from DM8806");
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return res;
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}
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return res;
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}
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static int phy_dm8806_reg_write(const struct device *dev, uint16_t phy_addr, uint16_t reg_addr,
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uint32_t data)
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{
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int res;
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const struct phy_dm8806_config *cfg = dev->config;
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res = mdio_write(cfg->mdio, phy_addr, reg_addr, data);
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if (res) {
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LOG_ERR("Failed to write data to DM8806");
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return res;
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}
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return res;
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}
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static const struct ethphy_driver_api phy_dm8806_api = {
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.get_link = phy_dm8806_get_link_state,
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.cfg_link = phy_dm8806_cfg_link,
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.link_cb_set = phy_dm8806_link_cb_set,
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.read = phy_dm8806_reg_read,
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.write = phy_dm8806_reg_write,
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};
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#define DM8806_PHY_DEFINE_CONFIG(n) \
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static const struct phy_dm8806_config phy_dm8806_config_##n = { \
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.mdio = DEVICE_DT_GET(DT_INST_BUS(n)), \
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.phy_addr = DT_INST_REG_ADDR(n), \
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.switch_addr = DT_PROP(DT_NODELABEL(dm8806_phy##n), reg_switch), \
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.gpio_int = GPIO_DT_SPEC_INST_GET(n, interrupt_gpio), \
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.gpio_rst = GPIO_DT_SPEC_INST_GET(n, reset_gpio), \
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}
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#define DM8806_PHY_INITIALIZE(n) \
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DM8806_PHY_DEFINE_CONFIG(n); \
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static struct phy_dm8806_data phy_dm8806_data_##n = { \
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.sem = Z_SEM_INITIALIZER(phy_dm8806_data_##n.sem, 1, 1), \
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}; \
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DEVICE_DT_INST_DEFINE(n, &phy_dm8806_init, NULL, &phy_dm8806_data_##n, \
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&phy_dm8806_config_##n, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY, \
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&phy_dm8806_api);
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DT_INST_FOREACH_STATUS_OKAY(DM8806_PHY_INITIALIZE)

‎drivers/ethernet/phy/phy_dm8806_priv.h

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/*
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* Copyright (c) 2024 Robert Slawinski <robert.slawinski1@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Port 0~4 PHY Control Register. */
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#define PORTX_PHY_CONTROL_REGISTER 0x0u
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/* 10 Mbit/s transfer with half duplex mask. */
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#define MODE_10_BASET_HALF_DUPLEX 0x0u
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/* 10 Mbit/s transfer with full duplex mask. */
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#define MODE_10_BASET_FULL_DUPLEX 0x100u
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/* 100 Mbit/s transfer with half duplex mask. */
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#define MODE_100_BASET_HALF_DUPLEX 0x2000u
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/* 100 Mbit/s transfer with full duplex mask. */
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#define MODE_100_BASET_FULL_DUPLEX 0x2100u
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/* Duplex mode ability offset. */
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#define DUPLEX_MODE (1 << 8)
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/* Power down mode offset. */
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#define POWER_DOWN (1 << 11)
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/* Auto negotiation mode offset. */
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#define AUTO_NEGOTIATION (1 << 12)
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/* Link speed selection offset. */
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#define LINK_SPEED (1 << 13)
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/* Port 0~4 Status Data Register. */
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#define PORTX_SWITCH_STATUS 0x10u
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/* 10 Mbit/s transfer speed with half duplex. */
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#define SPEED_10MBPS_HALF_DUPLEX 0x00u
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/* 10 Mbit/s transfer speed with full duplex. */
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#define SPEED_10MBPS_FULL_DUPLEX 0x01u
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/* 100 Mbit/s transfer speed with half duplex. */
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#define SPEED_100MBPS_HALF_DUPLEX 0x02u
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/* 100 Mbit/s transfer speed with full duplex. */
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#define SPEED_100MBPS_FULL_DUPLEX 0x03u
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/* Speed and duplex mode status offset. */
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#define SPEED_AND_DUPLEX_OFFSET 0x01u
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/* Speed and duplex mode staus mask. */
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#define SPEED_AND_DUPLEX_MASK 0x07u
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/* Link status mask. */
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#define LINK_STATUS_MASK 0x1u
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/* PHY address 0x18h */
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#define PHY_ADDRESS_18H 0x18u
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#define PORT5_MAC_CONTROL 0x15u
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/* Port 5 Force Speed control bit */
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#define P5_SPEED_100M ~BIT(0)
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/* Port 5 Force Duplex control bit */
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#define P5_FULL_DUPLEX ~BIT(1)
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/* Port 5 Force Link control bit. Only available in force mode. */
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#define P5_FORCE_LINK_ON ~BIT(2)
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/* Port 5 Force Mode Enable control bit. Only available for
54+
* MII/RevMII/RMII
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*/
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#define P5_EN_FORCE BIT(3)
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/* Bit 4 is reserved and should not be use */
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/* Port 5 50MHz Clock Output Enable control bit. Only available when Port 5
59+
* be configured as RMII
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*/
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#define P5_50M_CLK_OUT_ENABLE BIT(5)
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/* Port 5 Clock Source Selection control bit. Only available when Port 5
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* is configured as RMII
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*/
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#define P5_50M_INT_CLK_SOURCE BIT(6)
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/* Port 5 Output Pin Slew Rate. */
67+
#define P5_NORMAL_SLEW_RATE ~BIT(7)
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/* IRQ and LED Control Register. */
69+
#define IRQ_LED_CONTROL 0x17u
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/* LED mode 0:
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* LNK_LED:
72+
* 100M link fail - LED off
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* 100M link ok and no TX/RX activity - LED on
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* 100M link ok and TX/RX activity - LED blinking
75+
* SPD_LED:
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* No colision: - LED off
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* Colision: - LED blinking
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* FDX_LED:
79+
* 10M link fail - LED off
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* 10M link ok and no TX/RX activity - LED on
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* 10M link ok and TX/RX activity - LED blinking
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*/
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#define LED_MODE_0 ~(BIT(0) | BIT(1))

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