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Phuc Phamfabiobaltieri
Phuc Pham
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fabiobaltieri
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drivers: gpio: Add support for RZ/G2UL
Add GPIO support for RZ/G2UL Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com> Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
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‎drivers/gpio/gpio_renesas_rz.h

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414

1515
#if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL) || \
1616
defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L) || \
17-
defined(CONFIG_SOC_SERIES_RZV2H)
17+
defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZG2UL)
1818
#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
1919

2020
#if defined(CONFIG_SOC_SERIES_RZG3S)
@@ -75,6 +75,16 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {
7575
0, 2, 4, 6, 8, 10, 13, 15, 18, 21, 24, 25, 27, 29, 32, 34, 36,
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38, 41, 43, 45, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72,
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74, 76, 78, 80, 83, 85, 88, 91, 93, 98, 102, 106, 110, 114, 118};
78+
#elif defined(CONFIG_SOC_SERIES_RZG2UL)
79+
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P10)
80+
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM10)
81+
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC10)
82+
#define GPIO_RZ_MAX_PORT_NUM 19
83+
#define GPIO_RZ_TINT_IRQ_OFFSET 444
84+
#define R_INTC R_INTC_IM33
85+
#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC_IM33->TSCR &= ~BIT(tint_num))
86+
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43,
87+
47, 52, 56, 58, 63, 66, 70, 72, 76};
7888
#endif
7989

8090
#ifndef GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR

‎dts/arm/renesas/rz/rzg/r9a07g043.dtsi

Lines changed: 187 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,193 @@
3636
compatible = "renesas,rzg-pinctrl";
3737
reg = <0x41030000 DT_SIZE_K(64)>;
3838
reg-names = "pinctrl";
39+
40+
gpio: gpio-common {
41+
compatible = "renesas,rz-gpio-int";
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interrupts =
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<444 10>, <445 10>, <446 10>, <447 10>,
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<448 10>, <449 10>, <450 10>, <451 10>,
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<452 10>, <453 10>, <454 10>, <455 10>,
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<456 10>, <457 10>, <458 10>, <459 10>,
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<460 10>, <461 10>, <462 10>, <463 10>,
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<464 10>, <465 10>, <466 10>, <467 10>,
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<468 10>, <469 10>, <470 10>, <471 10>,
50+
<472 10>, <473 10>, <474 10>, <475 10>;
51+
#address-cells = <1>;
52+
#size-cells = <0>;
53+
status = "disabled";
54+
55+
gpio0: gpio@0 {
56+
compatible = "renesas,rz-gpio";
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gpio-controller;
58+
#gpio-cells = <2>;
59+
ngpios = <4>;
60+
reg = <0x0>;
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status = "disabled";
62+
};
63+
64+
gpio1: gpio@100 {
65+
compatible = "renesas,rz-gpio";
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gpio-controller;
67+
#gpio-cells= <2>;
68+
ngpios = <5>;
69+
reg = <0x100>;
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status = "disabled";
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};
72+
73+
gpio2: gpio@200 {
74+
compatible = "renesas,rz-gpio";
75+
gpio-controller;
76+
#gpio-cells= <2>;
77+
ngpios = <4>;
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reg = <0x200>;
79+
status = "disabled";
80+
};
81+
82+
gpio3: gpio@300 {
83+
compatible = "renesas,rz-gpio";
84+
gpio-controller;
85+
#gpio-cells= <2>;
86+
ngpios = <4>;
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reg = <0x300>;
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status = "disabled";
89+
};
90+
91+
gpio4: gpio@400 {
92+
compatible = "renesas,rz-gpio";
93+
gpio-controller;
94+
#gpio-cells= <2>;
95+
ngpios = <6>;
96+
reg = <0x400>;
97+
status = "disabled";
98+
};
99+
100+
gpio5: gpio@500 {
101+
compatible = "renesas,rz-gpio";
102+
gpio-controller;
103+
#gpio-cells= <2>;
104+
ngpios = <5>;
105+
reg = <0x500>;
106+
status = "disabled";
107+
};
108+
109+
gpio6: gpio@600 {
110+
compatible = "renesas,rz-gpio";
111+
gpio-controller;
112+
#gpio-cells= <2>;
113+
ngpios = <5>;
114+
reg = <0x600>;
115+
status = "disabled";
116+
};
117+
118+
gpio7: gpio@700 {
119+
compatible = "renesas,rz-gpio";
120+
gpio-controller;
121+
#gpio-cells= <2>;
122+
ngpios = <5>;
123+
reg = <0x700>;
124+
status = "disabled";
125+
};
126+
127+
gpio8: gpio@800 {
128+
compatible = "renesas,rz-gpio";
129+
gpio-controller;
130+
#gpio-cells= <2>;
131+
ngpios = <5>;
132+
reg = <0x800>;
133+
status = "disabled";
134+
};
135+
136+
gpio9: gpio@900 {
137+
compatible = "renesas,rz-gpio";
138+
gpio-controller;
139+
#gpio-cells= <2>;
140+
ngpios = <4>;
141+
reg = <0x900>;
142+
status = "disabled";
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};
144+
145+
gpio10: gpio@a00 {
146+
compatible = "renesas,rz-gpio";
147+
gpio-controller;
148+
#gpio-cells= <2>;
149+
ngpios = <5>;
150+
reg = <0xa00>;
151+
status = "disabled";
152+
};
153+
154+
gpio11: gpio@b00 {
155+
compatible = "renesas,rz-gpio";
156+
gpio-controller;
157+
#gpio-cells= <2>;
158+
ngpios = <4>;
159+
reg = <0xb00>;
160+
status = "disabled";
161+
};
162+
163+
gpio12: gpio@c00 {
164+
compatible = "renesas,rz-gpio";
165+
gpio-controller;
166+
#gpio-cells= <2>;
167+
ngpios = <2>;
168+
reg = <0xc00>;
169+
status = "disabled";
170+
};
171+
172+
gpio13: gpio@d00 {
173+
compatible = "renesas,rz-gpio";
174+
gpio-controller;
175+
#gpio-cells= <2>;
176+
ngpios = <5>;
177+
reg = <0xd00>;
178+
status = "disabled";
179+
};
180+
181+
gpio14: gpio@e00 {
182+
compatible = "renesas,rz-gpio";
183+
gpio-controller;
184+
#gpio-cells= <2>;
185+
ngpios = <3>;
186+
reg = <0xe00>;
187+
status = "disabled";
188+
};
189+
190+
gpio15: gpio@f00 {
191+
compatible = "renesas,rz-gpio";
192+
gpio-controller;
193+
#gpio-cells= <2>;
194+
ngpios = <4>;
195+
reg = <0xf00>;
196+
status = "disabled";
197+
};
198+
199+
gpio16: gpio@1000 {
200+
compatible = "renesas,rz-gpio";
201+
gpio-controller;
202+
#gpio-cells= <2>;
203+
ngpios = <2>;
204+
reg = <0x1000>;
205+
status = "disabled";
206+
};
207+
208+
gpio17: gpio@1100 {
209+
compatible = "renesas,rz-gpio";
210+
gpio-controller;
211+
#gpio-cells= <2>;
212+
ngpios = <4>;
213+
reg = <0x1100>;
214+
status = "disabled";
215+
};
216+
217+
gpio18: gpio@1200 {
218+
compatible = "renesas,rz-gpio";
219+
gpio-controller;
220+
#gpio-cells=<2>;
221+
ngpios = <6>;
222+
reg = <0x1200>;
223+
status = "disabled";
224+
};
225+
};
39226
};
40227

41228
scif0: serial@4004b800 {

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