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VynDragonVynDragon
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drivers: Add header file with common functions for BFLB
This moves the couple functions that are and will be all over the various clock operations for all platforms. Signed-off-by: Camille BAUD <mail@massdriver.space>
1 parent c906d4a commit 0f97ba5

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3 files changed

+77
-86
lines changed

3 files changed

+77
-86
lines changed

‎drivers/clock_control/clock_control_bl60x.c

Lines changed: 21 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ LOG_MODULE_REGISTER(clock_control_bl60x, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
2121
#include <bouffalolab/bl60x/pds_reg.h>
2222
#include <bouffalolab/bl60x/l1c_reg.h>
2323
#include <bouffalolab/bl60x/extra_defines.h>
24+
#include <zephyr/drivers/clock_control/clock_control_bflb_common.h>
2425

2526
#define CLK_SRC_IS(clk, src) \
2627
DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), 0), \
@@ -89,39 +90,6 @@ const static uint32_t clock_control_bl60x_crystal_SDMIN_table[5] = {
8990
0x49D39D,
9091
};
9192

92-
static inline void clock_control_bl60x_clock_settle(void)
93-
{
94-
__asm__ volatile(".rept 15 ; nop ; .endr");
95-
}
96-
97-
/* 32 Mhz Oscillator: 0
98-
* crystal: 1
99-
* PLL and 32M: 2
100-
* PLL and crystal: 3
101-
*/
102-
static void clock_control_bl60x_set_root_clock(uint32_t clock)
103-
{
104-
uint32_t tmp;
105-
106-
/* invalid value, fallback to internal 32M */
107-
if (clock > 3) {
108-
clock = 0;
109-
}
110-
tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
111-
tmp = (tmp & HBN_ROOT_CLK_SEL_UMSK) | (clock << HBN_ROOT_CLK_SEL_POS);
112-
sys_write32(tmp, HBN_BASE + HBN_GLB_OFFSET);
113-
114-
clock_control_bl60x_clock_settle();
115-
}
116-
117-
static uint32_t clock_control_bl60x_get_root_clock(void)
118-
{
119-
uint32_t tmp;
120-
121-
tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
122-
return (((tmp & HBN_ROOT_CLK_SEL_MSK) >> HBN_ROOT_CLK_SEL_POS) & 0x3);
123-
}
124-
12593
static int clock_control_bl60x_deinit_crystal(void)
12694
{
12795
uint32_t tmp;
@@ -132,7 +100,7 @@ static int clock_control_bl60x_deinit_crystal(void)
132100
tmp = tmp & AON_PU_XTAL_BUF_AON_UMSK;
133101
sys_write32(tmp, AON_BASE + AON_RF_TOP_AON_OFFSET);
134102

135-
clock_control_bl60x_clock_settle();
103+
clock_bflb_settle();
136104
return 0;
137105
}
138106

@@ -149,12 +117,12 @@ static int clock_control_bl60x_init_crystal(void)
149117

150118
/* wait for crystal to be powered on */
151119
do {
152-
clock_control_bl60x_clock_settle();
120+
clock_bflb_settle();
153121
tmp = sys_read32(AON_BASE + AON_TSEN_OFFSET);
154122
count--;
155123
} while (!(tmp & AON_XTAL_RDY_MSK) && count > 0);
156124

157-
clock_control_bl60x_clock_settle();
125+
clock_bflb_settle();
158126
if (count < 1) {
159127
return -1;
160128
}
@@ -167,11 +135,11 @@ static int clock_control_bl60x_set_root_clock_dividers(uint32_t hclk_div, uint32
167135
uint32_t tmp;
168136
uint32_t old_rootclk;
169137

170-
old_rootclk = clock_control_bl60x_get_root_clock();
138+
old_rootclk = clock_bflb_get_root_clock();
171139

172140
/* security RC32M */
173141
if (old_rootclk > 1) {
174-
clock_control_bl60x_set_root_clock(0);
142+
clock_bflb_set_root_clock(0);
175143
}
176144

177145
/* set dividers */
@@ -186,16 +154,16 @@ static int clock_control_bl60x_set_root_clock_dividers(uint32_t hclk_div, uint32
186154
sys_write32(0x00000001, 0x40000FFC);
187155
sys_write32(0x00000000, 0x40000FFC);
188156

189-
clock_control_bl60x_clock_settle();
157+
clock_bflb_settle();
190158

191159
/* enable clocks */
192160
tmp = sys_read32(GLB_BASE + GLB_CLK_CFG0_OFFSET);
193161
tmp = (tmp & GLB_REG_BCLK_EN_UMSK) | (1U << GLB_REG_BCLK_EN_POS);
194162
tmp = (tmp & GLB_REG_HCLK_EN_UMSK) | (1U << GLB_REG_HCLK_EN_POS);
195163
sys_write32(tmp, GLB_BASE + GLB_CLK_CFG0_OFFSET);
196164

197-
clock_control_bl60x_set_root_clock(old_rootclk);
198-
clock_control_bl60x_clock_settle();
165+
clock_bflb_set_root_clock(old_rootclk);
166+
clock_bflb_settle();
199167

200168
return 0;
201169
}
@@ -284,11 +252,11 @@ static void clock_control_bl60x_init_pll(enum bl60x_clkid source, uint32_t cryst
284252
uint32_t tmp;
285253
uint32_t old_rootclk;
286254

287-
old_rootclk = clock_control_bl60x_get_root_clock();
255+
old_rootclk = clock_bflb_get_root_clock();
288256

289257
/* security RC32M */
290258
if (old_rootclk > 1) {
291-
clock_control_bl60x_set_root_clock(0);
259+
clock_bflb_set_root_clock(0);
292260
}
293261

294262
clock_control_bl60x_deinit_pll();
@@ -356,7 +324,7 @@ static void clock_control_bl60x_init_pll(enum bl60x_clkid source, uint32_t cryst
356324
tmp = sys_read32(PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
357325
tmp = (tmp & PDS_PU_CLKPLL_SFREG_UMSK) | (1U << PDS_PU_CLKPLL_SFREG_POS);
358326
sys_write32(tmp, PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
359-
clock_control_bl60x_clock_settle();
327+
clock_bflb_settle();
360328

361329
/* enable PPL clock actual? */
362330
tmp = sys_read32(PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
@@ -371,7 +339,7 @@ static void clock_control_bl60x_init_pll(enum bl60x_clkid source, uint32_t cryst
371339
tmp = (tmp & PDS_CLKPLL_PU_POSTDIV_UMSK) | (1U << PDS_CLKPLL_PU_POSTDIV_POS);
372340
sys_write32(tmp, PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
373341

374-
clock_control_bl60x_clock_settle();
342+
clock_bflb_settle();
375343

376344
/* reset couple things one by one? */
377345
tmp = sys_read32(PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
@@ -390,8 +358,8 @@ static void clock_control_bl60x_init_pll(enum bl60x_clkid source, uint32_t cryst
390358
tmp = (tmp & PDS_CLKPLL_SDM_RESET_UMSK) | (0U << PDS_CLKPLL_SDM_RESET_POS);
391359
sys_write32(tmp, PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
392360

393-
clock_control_bl60x_set_root_clock(old_rootclk);
394-
clock_control_bl60x_clock_settle();
361+
clock_bflb_set_root_clock(old_rootclk);
362+
clock_bflb_settle();
395363
}
396364

397365
/*
@@ -439,7 +407,7 @@ static int clock_control_bl60x_clock_trim_32M(void)
439407
tmp = (tmp & PDS_RC32M_CODE_FR_EXT_UMSK) | trim << PDS_RC32M_CODE_FR_EXT_POS;
440408
sys_write32(tmp, PDS_BASE + PDS_RC32M_CTRL0_OFFSET);
441409

442-
clock_control_bl60x_clock_settle();
410+
clock_bflb_settle();
443411

444412
return 0;
445413
}
@@ -557,9 +525,9 @@ static void clock_control_bl60x_init_root_as_pll(const struct device *dev)
557525
clock_control_bl60x_select_PLL(data->root.pll_select);
558526

559527
if (data->pll.source == bl60x_clkid_clk_crystal) {
560-
clock_control_bl60x_set_root_clock(3);
528+
clock_bflb_set_root_clock(3);
561529
} else {
562-
clock_control_bl60x_set_root_clock(2);
530+
clock_bflb_set_root_clock(2);
563531
}
564532

565533
if (clock_control_bl60x_get_clk(dev) > MHZ(120)) {
@@ -572,7 +540,7 @@ static void clock_control_bl60x_init_root_as_pll(const struct device *dev)
572540

573541
static void clock_control_bl60x_init_root_as_crystal(const struct device *dev)
574542
{
575-
clock_control_bl60x_set_root_clock(1);
543+
clock_bflb_set_root_clock(1);
576544
sys_write32(clock_control_bl60x_get_clk(dev), CORECLOCKREGISTER);
577545
}
578546

@@ -590,7 +558,7 @@ static int clock_control_bl60x_update_root(const struct device *dev)
590558
sys_write32(tmp, GLB_BASE + GLB_CLK_CFG0_OFFSET);
591559

592560
/* set root clock to internal 32MHz Oscillator as failsafe */
593-
clock_control_bl60x_set_root_clock(0);
561+
clock_bflb_set_root_clock(0);
594562
if (clock_control_bl60x_set_root_clock_dividers(0, 0) != 0) {
595563
return -EIO;
596564
}
@@ -627,7 +595,7 @@ static int clock_control_bl60x_update_root(const struct device *dev)
627595
clock_control_bl60x_set_machine_timer_clock(
628596
1, 0, clock_control_bl60x_mtimer_get_clk_src_div(dev));
629597

630-
clock_control_bl60x_clock_settle();
598+
clock_bflb_settle();
631599

632600
return ret;
633601
}

‎drivers/syscon/syscon_bflb_efuse.c

Lines changed: 8 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ LOG_MODULE_REGISTER(efuse_bflb, CONFIG_SYSCON_LOG_LEVEL);
1616
#include <bouffalolab/bl60x/hbn_reg.h>
1717
#include <bouffalolab/bl60x/ef_ctrl_reg.h>
1818
#include <bouffalolab/bl60x/extra_defines.h>
19+
#include <zephyr/drivers/clock_control/clock_control_bflb_common.h>
1920

2021
struct efuse_bflb_data {
2122
uint8_t cache[DT_INST_PROP(0, size)];
@@ -27,31 +28,6 @@ struct efuse_bflb_config {
2728
size_t size;
2829
};
2930

30-
static inline void efuse_bflb_clock_settle(void)
31-
{
32-
__asm__ volatile (".rept 15 ; nop ; .endr");
33-
}
34-
35-
/* 32 Mhz Oscillator: 0
36-
* crystal: 1
37-
* PLL and 32M: 2
38-
* PLL and crystal: 3
39-
*/
40-
static void efuse_bflb_set_root_clock(uint32_t clock)
41-
{
42-
uint32_t tmp;
43-
44-
/* invalid value, fallback to internal 32M */
45-
if (clock > 3) {
46-
clock = 0;
47-
}
48-
tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
49-
tmp = (tmp & HBN_ROOT_CLK_SEL_UMSK) | (clock << HBN_ROOT_CLK_SEL_POS);
50-
sys_write32(tmp, HBN_BASE + HBN_GLB_OFFSET);
51-
52-
efuse_bflb_clock_settle();
53-
}
54-
5531
static void efuse_bflb_clock_delay_32M_ms(uint32_t ms)
5632
{
5733
uint32_t count = 0;
@@ -107,7 +83,7 @@ static void efuse_bflb_efuse_read(const struct device *dev)
10783
| (0 << EF_CTRL_EF_IF_0_TRIG_POS);
10884

10985
sys_write32(tmp, config->addr + EF_CTRL_EF_IF_CTRL_0_OFFSET);
110-
efuse_bflb_clock_settle();
86+
clock_bflb_settle();
11187

11288
/* clear PDS cache registry */
11389
for (uint32_t i = 0; i < config->size / 4; i++) {
@@ -172,13 +148,12 @@ static void efuse_bflb_cache(const struct device *dev)
172148
struct efuse_bflb_data *data = dev->data;
173149
const struct efuse_bflb_config *config = dev->config;
174150
uint32_t tmp;
175-
uint8_t old_clock_root;
151+
uint32_t old_clock_root;
176152

177-
tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
178-
old_clock_root = (tmp & HBN_ROOT_CLK_SEL_MSK) >> HBN_ROOT_CLK_SEL_POS;
153+
old_clock_root = clock_bflb_get_root_clock();
179154

180-
efuse_bflb_set_root_clock(0);
181-
efuse_bflb_clock_settle();
155+
clock_bflb_set_root_clock(0);
156+
clock_bflb_settle();
182157

183158
efuse_bflb_efuse_read(dev);
184159
/* reads *must* be 32-bits aligned AND does not work with the method memcpy uses */
@@ -190,8 +165,8 @@ static void efuse_bflb_cache(const struct device *dev)
190165
data->cache[i * sizeof(uint32_t) + 0] = (tmp & 0x000000FFU);
191166
}
192167

193-
efuse_bflb_set_root_clock(old_clock_root);
194-
efuse_bflb_clock_settle();
168+
clock_bflb_set_root_clock(old_clock_root);
169+
clock_bflb_settle();
195170
data->cached = true;
196171
}
197172

‎include/zephyr/drivers/clock_control/clock_control_bflb_common.h

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
/*
2+
* Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/* Contains short functions relevant to timing and clocks common to all Bouffalolab platforms */
8+
9+
#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_BFLB_COMMON_H_
10+
#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_BFLB_COMMON_H_
11+
12+
/* Function that busy waits for a few cycles */
13+
static inline void clock_bflb_settle(void)
14+
{
15+
__asm__ volatile (".rept 20 ; nop ; .endr");
16+
}
17+
18+
/* Common main clock mux
19+
*
20+
* 32 Mhz Oscillator: 0 (using XCLK)
21+
* crystal: 1 (using XCLK)
22+
* PLL and 32M: 2 (using PLL mux, XCLK is 32M)
23+
* PLL and crystal: 3 (using PLL mux, XCLK is crystal)
24+
*/
25+
static inline void clock_bflb_set_root_clock(uint32_t clock)
26+
{
27+
uint32_t tmp;
28+
29+
/* invalid value, fallback to internal 32M */
30+
if (clock > 3) {
31+
clock = 0;
32+
}
33+
tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
34+
tmp = (tmp & HBN_ROOT_CLK_SEL_UMSK) | (clock << HBN_ROOT_CLK_SEL_POS);
35+
sys_write32(tmp, HBN_BASE + HBN_GLB_OFFSET);
36+
37+
clock_bflb_settle();
38+
}
39+
40+
static inline uint32_t clock_bflb_get_root_clock(void)
41+
{
42+
uint32_t tmp;
43+
44+
tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
45+
return (((tmp & HBN_ROOT_CLK_SEL_MSK) >> HBN_ROOT_CLK_SEL_POS) & 0x3);
46+
}
47+
48+
#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_BFLB_COMMON_H_ */

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