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drivers: spi: litex: remove core_ prefix
remove `core_` prefix from code and register names, got dropped in litex in enjoy-digital/litex#2253 Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
1 parent e38d067 commit 0e3ee4c

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+52
-52
lines changed

2 files changed

+52
-52
lines changed

‎drivers/spi/spi_litex_litespi.c

Lines changed: 47 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -18,12 +18,12 @@ LOG_MODULE_REGISTER(spi_litex_litespi);
1818

1919
#define SPI_LITEX_HAS_IRQ (SPI_LITEX_ALL_HAS_IRQ || dev_config->has_irq)
2020

21-
#define SPIFLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET 0x0
22-
#define SPIFLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET 0x1
23-
#define SPIFLASH_CORE_MASTER_PHYCONFIG_MASK_OFFSET 0x2
21+
#define SPIFLASH_MASTER_PHYCONFIG_LEN_OFFSET 0x0
22+
#define SPIFLASH_MASTER_PHYCONFIG_WIDTH_OFFSET 0x1
23+
#define SPIFLASH_MASTER_PHYCONFIG_MASK_OFFSET 0x2
2424

25-
#define SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET 0x0
26-
#define SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET 0x1
25+
#define SPIFLASH_MASTER_STATUS_TX_READY_OFFSET 0x0
26+
#define SPIFLASH_MASTER_STATUS_RX_READY_OFFSET 0x1
2727

2828
#define SPI_MAX_WORD_SIZE 32
2929
#define SPI_MAX_CS_SIZE 4
@@ -32,18 +32,18 @@ LOG_MODULE_REGISTER(spi_litex_litespi);
3232
#define SPI_LITEX_MASK BIT(0)
3333

3434
struct spi_litex_dev_config {
35-
uint32_t core_master_cs_addr;
36-
uint32_t core_master_phyconfig_addr;
37-
uint32_t core_master_rxtx_addr;
38-
uint32_t core_master_rxtx_size;
39-
uint32_t core_master_status_addr;
35+
uint32_t master_cs_addr;
36+
uint32_t master_phyconfig_addr;
37+
uint32_t master_rxtx_addr;
38+
uint32_t master_rxtx_size;
39+
uint32_t master_status_addr;
4040
uint32_t phy_clk_divisor_addr;
4141
bool phy_clk_divisor_exists;
4242
#if SPI_LITEX_ANY_HAS_IRQ
4343
bool has_irq;
4444
void (*irq_config_func)(const struct device *dev);
45-
uint32_t core_master_ev_pending_addr;
46-
uint32_t core_master_ev_enable_addr;
45+
uint32_t master_ev_pending_addr;
46+
uint32_t master_ev_enable_addr;
4747
#endif
4848
};
4949

@@ -135,12 +135,12 @@ static void spiflash_len_mask_width_write(uint32_t len, uint32_t width, uint32_t
135135
uint32_t addr)
136136
{
137137
uint32_t tmp = len & BIT_MASK(8);
138-
uint32_t word = tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET * 8);
138+
uint32_t word = tmp << (SPIFLASH_MASTER_PHYCONFIG_LEN_OFFSET * 8);
139139

140140
tmp = width & BIT_MASK(8);
141-
word |= tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET * 8);
141+
word |= tmp << (SPIFLASH_MASTER_PHYCONFIG_WIDTH_OFFSET * 8);
142142
tmp = mask & BIT_MASK(8);
143-
word |= tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_MASK_OFFSET * 8);
143+
word |= tmp << (SPIFLASH_MASTER_PHYCONFIG_MASK_OFFSET * 8);
144144
litex_write32(word, addr);
145145
}
146146

@@ -152,10 +152,10 @@ static void spi_litex_spi_do_tx(const struct device *dev)
152152
uint8_t len;
153153
uint32_t txd = 0U;
154154

155-
len = MIN(spi_context_max_continuous_chunk(ctx), dev_config->core_master_rxtx_size);
155+
len = MIN(spi_context_max_continuous_chunk(ctx), dev_config->master_rxtx_size);
156156
if (len != data->len) {
157157
spiflash_len_mask_width_write(len * 8, SPI_LITEX_WIDTH, SPI_LITEX_MASK,
158-
dev_config->core_master_phyconfig_addr);
158+
dev_config->master_phyconfig_addr);
159159
data->len = len;
160160
}
161161

@@ -164,7 +164,7 @@ static void spi_litex_spi_do_tx(const struct device *dev)
164164
}
165165

166166
LOG_DBG("txd: 0x%x", txd);
167-
litex_write32(txd, dev_config->core_master_rxtx_addr);
167+
litex_write32(txd, dev_config->master_rxtx_addr);
168168

169169
spi_context_update_tx(ctx, data->dfs, len / data->dfs);
170170
}
@@ -176,7 +176,7 @@ static void spi_litex_spi_do_rx(const struct device *dev)
176176
struct spi_context *ctx = &data->ctx;
177177
uint32_t rxd;
178178

179-
rxd = litex_read32(dev_config->core_master_rxtx_addr);
179+
rxd = litex_read32(dev_config->master_rxtx_addr);
180180
LOG_DBG("rxd: 0x%x", rxd);
181181

182182
if (spi_context_rx_buf_on(ctx)) {
@@ -193,24 +193,24 @@ static int spi_litex_xfer(const struct device *dev, const struct spi_config *con
193193
struct spi_context *ctx = &data->ctx;
194194
uint32_t rxd;
195195

196-
litex_write32(BIT(config->slave), dev_config->core_master_cs_addr);
196+
litex_write32(BIT(config->slave), dev_config->master_cs_addr);
197197

198198
/* Flush RX buffer */
199-
while ((litex_read8(dev_config->core_master_status_addr) &
200-
BIT(SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET))) {
201-
rxd = litex_read32(dev_config->core_master_rxtx_addr);
199+
while ((litex_read8(dev_config->master_status_addr) &
200+
BIT(SPIFLASH_MASTER_STATUS_RX_READY_OFFSET))) {
201+
rxd = litex_read32(dev_config->master_rxtx_addr);
202202
LOG_DBG("flushed rxd: 0x%x", rxd);
203203
}
204204

205-
while (!(litex_read8(dev_config->core_master_status_addr) &
206-
BIT(SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET))) {
205+
while (!(litex_read8(dev_config->master_status_addr) &
206+
BIT(SPIFLASH_MASTER_STATUS_TX_READY_OFFSET))) {
207207
;
208208
}
209209

210210
#if SPI_LITEX_ANY_HAS_IRQ
211211
if (SPI_LITEX_HAS_IRQ) {
212-
litex_write8(BIT(0), dev_config->core_master_ev_enable_addr);
213-
litex_write8(BIT(0), dev_config->core_master_ev_pending_addr);
212+
litex_write8(BIT(0), dev_config->master_ev_enable_addr);
213+
litex_write8(BIT(0), dev_config->master_ev_pending_addr);
214214

215215
spi_litex_spi_do_tx(dev);
216216

@@ -221,15 +221,15 @@ static int spi_litex_xfer(const struct device *dev, const struct spi_config *con
221221
do {
222222
spi_litex_spi_do_tx(dev);
223223

224-
while (!(litex_read8(dev_config->core_master_status_addr) &
225-
BIT(SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET))) {
224+
while (!(litex_read8(dev_config->master_status_addr) &
225+
BIT(SPIFLASH_MASTER_STATUS_RX_READY_OFFSET))) {
226226
;
227227
}
228228

229229
spi_litex_spi_do_rx(dev);
230230
} while (spi_context_tx_on(ctx) || spi_context_rx_on(ctx));
231231

232-
litex_write32(0, dev_config->core_master_cs_addr);
232+
litex_write32(0, dev_config->master_cs_addr);
233233

234234
spi_context_complete(ctx, dev, 0);
235235

@@ -311,18 +311,18 @@ static void spi_litex_irq_handler(const struct device *dev)
311311
const struct spi_litex_dev_config *dev_config = dev->config;
312312
struct spi_context *ctx = &data->ctx;
313313

314-
if (litex_read8(dev_config->core_master_ev_pending_addr) & BIT(0)) {
314+
if (litex_read8(dev_config->master_ev_pending_addr) & BIT(0)) {
315315
spi_litex_spi_do_rx(dev);
316316

317317
/* ack reader irq */
318-
litex_write8(BIT(0), dev_config->core_master_ev_pending_addr);
318+
litex_write8(BIT(0), dev_config->master_ev_pending_addr);
319319

320320
if (spi_context_tx_on(ctx) || spi_context_rx_on(ctx)) {
321321
spi_litex_spi_do_tx(dev);
322322
} else {
323-
litex_write8(0, dev_config->core_master_ev_enable_addr);
323+
litex_write8(0, dev_config->master_ev_enable_addr);
324324

325-
litex_write32(0, dev_config->core_master_cs_addr);
325+
litex_write32(0, dev_config->master_cs_addr);
326326

327327
spi_context_complete(ctx, dev, 0);
328328
}
@@ -364,8 +364,8 @@ static DEVICE_API(spi, spi_litex_api) = {
364364
};
365365

366366
#define SPI_LITEX_IRQ(n) \
367-
BUILD_ASSERT(DT_INST_REG_HAS_NAME(n, core_master_ev_pending) && \
368-
DT_INST_REG_HAS_NAME(n, core_master_ev_enable), "registers for interrupts missing"); \
367+
BUILD_ASSERT(DT_INST_REG_HAS_NAME(n, master_ev_pending) && \
368+
DT_INST_REG_HAS_NAME(n, master_ev_enable), "registers for interrupts missing"); \
369369
\
370370
static void spi_litex_irq_config##n(const struct device *dev) \
371371
{ \
@@ -379,8 +379,8 @@ static DEVICE_API(spi, spi_litex_api) = {
379379
.has_irq = DT_INST_IRQ_HAS_IDX(n, 0), \
380380
.irq_config_func = COND_CODE_1(DT_INST_IRQ_HAS_IDX(n, 0), \
381381
(spi_litex_irq_config##n), (NULL)), \
382-
.core_master_ev_pending_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, core_master_ev_pending, 0), \
383-
.core_master_ev_enable_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, core_master_ev_enable, 0),
382+
.master_ev_pending_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, master_ev_pending, 0), \
383+
.master_ev_enable_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, master_ev_enable, 0),
384384

385385
#define SPI_INIT(n) \
386386
IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), (SPI_LITEX_IRQ(n))) \
@@ -390,16 +390,16 @@ static DEVICE_API(spi, spi_litex_api) = {
390390
SPI_CONTEXT_INIT_SYNC(spi_litex_data_##n, ctx), \
391391
}; \
392392
\
393-
static struct spi_litex_dev_config spi_litex_cfg_##n = { \
394-
.core_master_cs_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_cs), \
395-
.core_master_phyconfig_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_phyconfig), \
396-
.core_master_rxtx_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_rxtx), \
397-
.core_master_rxtx_size = DT_INST_REG_SIZE_BY_NAME(n, core_master_rxtx), \
398-
.core_master_status_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_status), \
399-
.phy_clk_divisor_exists = DT_INST_REG_HAS_NAME(n, phy_clk_divisor), \
400-
.phy_clk_divisor_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, phy_clk_divisor, 0), \
393+
static struct spi_litex_dev_config spi_litex_cfg_##n = { \
394+
.master_cs_addr = DT_INST_REG_ADDR_BY_NAME(n, master_cs), \
395+
.master_phyconfig_addr = DT_INST_REG_ADDR_BY_NAME(n, master_phyconfig), \
396+
.master_rxtx_addr = DT_INST_REG_ADDR_BY_NAME(n, master_rxtx), \
397+
.master_rxtx_size = DT_INST_REG_SIZE_BY_NAME(n, master_rxtx), \
398+
.master_status_addr = DT_INST_REG_ADDR_BY_NAME(n, master_status), \
399+
.phy_clk_divisor_exists = DT_INST_REG_HAS_NAME(n, phy_clk_divisor), \
400+
.phy_clk_divisor_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, phy_clk_divisor, 0), \
401401
IF_ENABLED(SPI_LITEX_ANY_HAS_IRQ, (SPI_LITEX_IRQ_CONFIG(n))) \
402-
}; \
402+
}; \
403403
\
404404
SPI_DEVICE_DT_INST_DEFINE(n, \
405405
spi_litex_init, NULL, &spi_litex_data_##n, &spi_litex_cfg_##n, POST_KERNEL, \

‎dts/riscv/riscv32-litex-vexriscv.dtsi

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -102,11 +102,11 @@
102102
<0xe000c010 0x4>,
103103
<0xe000c800 0x4>,
104104
<0x60000000 0x1000000>;
105-
reg-names = "core_mmap_dummy_bits",
106-
"core_master_cs",
107-
"core_master_phyconfig",
108-
"core_master_rxtx",
109-
"core_master_status",
105+
reg-names = "mmap_dummy_bits",
106+
"master_cs",
107+
"master_phyconfig",
108+
"master_rxtx",
109+
"master_status",
110110
"phy_clk_divisor",
111111
"flash_mmap";
112112
#address-cells = <1>;

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