soc: wch: work-around a bug in wfi in the QingKe V2A

The RISC-V Machine-Level ISA section 3.3.3 says that `wfi` will
complete even if interrupts are masked, but the QingKe V2A does not do
this. Work-around by enabling interrupts first.

This is the same mitigation as used for the Nordic VPR.

Signed-off-by: Michael Hope <michaelh@juju.nz>
Co-authored-by: Pete Johanson <peter@peterjohanson.com>

Author: nzmichaelh

drivers/interrupt_controller/intc_wch_pfic.c

@@ -34,10 +34,6 @@ int arch_irq_is_enabled(unsigned int irq)
 
 static int pfic_init(void)
 {
-	/* `wfi` is called with interrupts disabled. Configure the PFIC to wake up on any event,
-	 * including any interrupt.
-	 */
-	PFIC->SCTLR = SEVONPEND | WFITOWFE;
 	return 0;
 }
 

soc/wch/ch32v/CMakeLists.txt

@@ -1,6 +1,7 @@
 # Copyright (c) 2024 Michael Hope
 # SPDX-License-Identifier: Apache-2.0
 
+add_subdirectory(common)
 add_subdirectory(${SOC_SERIES})
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/wch/ch32v/common/soc_idle.c

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2025 Michael Hope <michaelh@juju.nz>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/irq.h>
+#include <zephyr/tracing/tracing.h>
+
+void arch_cpu_idle(void)
+{
+	/*
+	 * The RISC-V Machine-Level ISA section 3.3.3 says that `wfi` will complete even if
+	 * interrupts are masked, but the QingKe V2A does not do this. Work-around by enabling
+	 * interrupts first.
+	 */
+	sys_trace_idle();
+	irq_unlock(MSTATUS_IEN);
+	__asm__ volatile("wfi");
+	sys_trace_idle_exit();
+}
+
+void arch_cpu_atomic_idle(unsigned int key)
+{
+	sys_trace_idle();
+	irq_unlock(key);
+	__asm__ volatile("wfi");
+	sys_trace_idle_exit();
+}

soc/wch/ch32v/qingke_v2a/Kconfig

@@ -6,3 +6,6 @@ config SOC_SERIES_QINGKE_V2A
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_ISA_EXT_C
+	select RISCV_ALWAYS_SWITCH_THROUGH_ECALL
+	select ARCH_HAS_CUSTOM_CPU_IDLE
+	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE

soc/wch/ch32v/qingke_v4b/Kconfig

@@ -8,3 +8,6 @@ config SOC_SERIES_QINGKE_V4B
 	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_ALWAYS_SWITCH_THROUGH_ECALL
+	select ARCH_HAS_CUSTOM_CPU_IDLE
+	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE

soc/wch/ch32v/qingke_v4c/Kconfig

@@ -8,3 +8,6 @@ config SOC_SERIES_QINGKE_V4C
 	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_ALWAYS_SWITCH_THROUGH_ECALL
+	select ARCH_HAS_CUSTOM_CPU_IDLE
+	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE

soc/wch/ch32v/qingke_v4f/Kconfig

@@ -9,3 +9,6 @@ config SOC_SERIES_QINGKE_V4F
 	select RISCV_ISA_EXT_F
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_ALWAYS_SWITCH_THROUGH_ECALL
+	select ARCH_HAS_CUSTOM_CPU_IDLE
+	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE

soc/wch/ch32v/qingke_v4f/Kconfig.defconfig

@@ -9,6 +9,9 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config CLOCK_CONTROL
 	default y
 
+config ISR_TABLES_LOCAL_DECLARATION_SUPPORTED
+	default n
+
 rsource "Kconfig.defconfig.*"
 
 endif # SOC_SERIES_QINGKE_V4F

soc/wch/ch32v/qingke_v4f/vector.S

@@ -22,11 +22,17 @@ SECTION_FUNC(vectors, ivt)
 	lui	x5, 0x8000
 	jr	0x8(x5)
 	j       __start
+_irq_vector_table:
 	.rept   CONFIG_VECTOR_TABLE_SIZE
 	.word	_isr_wrapper
 	.endr
 
 SECTION_FUNC(vectors, __start)
-	li 	a0, 0xf
+	li      a0, 0x1f
+	csrw    0xbc0, a0
+	li      a0, 0x1e
+	csrw    0x804, a0
+	la t0, _irq_vector_table /* Load address of interrupt vector table */
+	ori t0, t0, 0x03
 	csrw	mtvec, a0
 	j	__initialize