dts: arm: microchip: Fixes in preparation for boards

We fixed some minor bugs and one missing component for
Microchip MEC5 HAL based chips, MEC174x and MEC175x.
These changes are in preparation for board check-in and
hello world sample. Added the clock-frequency property
to the cpu and rtimer nodes. This properity is used
derive the Kconfig's for the kernel tick.

Signed-off-by: Scott Worley <scott.worley@microchip.com>

Author: scottwcpg

dts/arm/microchip/mec1501hsz.dtsi

@@ -20,6 +20,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-m4";
 			reg = <0>;
+			clock-frequency = <48000000>;
 			cpu-power-states = <&idle &suspend_to_ram>;
 		};
 
@@ -160,6 +161,7 @@
 			compatible = "microchip,xec-rtos-timer";
 			reg = <0x40007400 0x10>;
 			interrupts = <111 0>;
+			clock-frequency = <32768>;
 			girqs = <23 10>;
 		};
 		bbram: bb-ram@4000a800 {

dts/arm/microchip/mec172x_common.dtsi

@@ -290,6 +290,7 @@ rtimer: timer@40007400 {
 	compatible = "microchip,xec-rtos-timer";
 	reg = <0x40007400 0x10>;
 	interrupts = <111 0>;
+	clock-frequency = <32768>;
 	girqs = <23 10>;
 };
 timer0: timer@40000c00 {

dts/arm/microchip/mec172xnlj.dtsi

@@ -26,6 +26,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-m4";
 			reg = <0>;
+			clock-frequency = <96000000>;
 			cpu-power-states = <&idle &suspend_to_ram>;
 		};
 

dts/arm/microchip/mec172xnsz.dtsi

@@ -26,6 +26,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-m4";
 			reg = <0>;
+			clock-frequency = <96000000>;
 			cpu-power-states = <&idle &suspend_to_ram>;
 		};
 

dts/arm/microchip/mec5.dtsi

@@ -7,6 +7,7 @@
 #include <arm/armv7-m.dtsi>
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
 #include <freq.h>
 #include <mem.h>
 
@@ -19,6 +20,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-m4";
 			reg = <0>;
+			clock-frequency = <96000000>;
 		};
 	};
 
@@ -202,7 +204,7 @@
 			interrupts = <41 1>;
 			status = "disabled";
 		};
-		wdog: watchdog@40000400 {
+		watchdog0: watchdog@40000400 {
 			reg = <0x40000400 0x400>;
 			interrupts = <171 0>;
 			status = "disabled";
@@ -311,7 +313,7 @@
 			status = "disabled";
 		};
 		bbram: bb-ram@4000a800 {
-			reg = <0x4000a800 0x100>;
+			reg = <0x4000a800 0x80>;
 			reg-names = "memory";
 			status = "disabled";
 		};

dts/arm/microchip/mec5/mec5_i3c.dtsi

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Microchip MEC5 SoC's Improved I2C(I3C).
+ * Include this file in the soc {} section in the relevant chip DTSI files.
+ */
+i3c0: i3c@40010800 {
+	compatible = "microchip,mec5-i3c";
+	#address-cells = <3>;
+	#size-cells = <0>;
+	reg = <0x40010800 0x800>;
+	interrupts = <181 2>;
+	input-clock-frequency = <192000000>;
+	i3c-scl-hz = <12500000>;
+	i2c-scl-hz = <400000>;
+	status = "disabled";
+};
+
+i3c1: i3c@40010000 {
+	compatible = "microchip,mec5-i3c";
+	#address-cells = <3>;
+	#size-cells = <0>;
+	reg = <0x40010000 0x800>;
+	interrupts = <182 2>;
+	input-clock-frequency = <192000000>;
+	i3c-scl-hz = <12500000>;
+	i2c-scl-hz = <400000>;
+	status = "disabled";
+};

dts/arm/microchip/mec5_mec1753qsz.dtsi

@@ -7,7 +7,6 @@
 #include <arm/armv7-m.dtsi>
 
 #include "mec5.dtsi"
-#include "mec5/mec5_mec175xsz-espi-host-dev.dtsi"
 
 / {
 	flash0: flash@b0000 {

dts/bindings/timer/microchip,xec-rtos-timer.yaml

@@ -18,3 +18,9 @@ properties:
     type: array
     required: true
     description: Array of GIRQ numbers [8:26] and bit positions [0:31].
+
+  clock-frequency:
+    type: int
+    required: true
+    const: 32768
+    description: RTOS timer runs at fixed 32 KHz.