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RtkFPcaiyi_zhong
RtkFP
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caiyi_zhong
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drivers: reset: add reset driver for RTS5817
Add reset driver for RTS5817 Signed-off-by: Darcy Lu <darcy_lu@realsil.com.cn>
1 parent 6ded4c1 commit 037bb01

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‎drivers/reset/CMakeLists.txt

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@@ -13,3 +13,4 @@ zephyr_library_sources_ifdef(CONFIG_RESET_NPCX reset_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_NXP_SYSCON reset_lpc_syscon.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_NXP_RSTCTL reset_nxp_rstctl.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_MMIO reset_mmio.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_RTS5817 reset_rts5817.c)

‎drivers/reset/Kconfig

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@@ -37,5 +37,6 @@ rsource "Kconfig.npcx"
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rsource "Kconfig.lpc_syscon"
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rsource "Kconfig.nxp_rstctl"
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rsource "Kconfig.mmio"
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rsource "Kconfig.rts5817"
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endif # RESET

‎drivers/reset/Kconfig.rts5817

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# Copyright (c) 2024 Realtek Semiconductor, Inc.
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# SPDX-License-Identifier: Apache-2.0
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config RESET_RTS5817
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bool "RTS5817 Reset Controller Driver"
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default y
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depends on DT_HAS_REALTEK_RTS5817_RESET_ENABLED
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help
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This option enables the reset controller driver for RTS5817.

‎drivers/reset/reset_rts5817.c

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/*
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* Copyright (c) 2024 Realtek Semiconductor, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT realtek_rts5817_reset
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/reset.h>
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#include "reset_rts5817.h"
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struct reset_rts5817_config {
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uintptr_t base;
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};
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static int reset_rts5817_status(const struct device *dev, uint32_t id, uint8_t *status)
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{
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const struct reset_rts5817_config *config = dev->config;
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*status = !!sys_test_bit(config->base + R_SYS_FORCE_RST, id);
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return 0;
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}
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static int reset_rts5817_line_assert(const struct device *dev, uint32_t id)
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{
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const struct reset_rts5817_config *config = dev->config;
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sys_set_bit(config->base + R_SYS_FORCE_RST, id);
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return 0;
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}
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static int reset_rts5817_line_deassert(const struct device *dev, uint32_t id)
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{
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const struct reset_rts5817_config *config = dev->config;
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sys_clear_bit(config->base + R_SYS_FORCE_RST, id);
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return 0;
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}
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static int reset_rts5817_line_toggle(const struct device *dev, uint32_t id)
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{
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reset_rts5817_line_assert(dev, id);
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reset_rts5817_line_deassert(dev, id);
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return 0;
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}
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static const struct reset_driver_api reset_rts5817_driver_api = {
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.status = reset_rts5817_status,
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.line_assert = reset_rts5817_line_assert,
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.line_deassert = reset_rts5817_line_deassert,
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.line_toggle = reset_rts5817_line_toggle,
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};
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static const struct reset_rts5817_config reset_rts5817_config = {
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.base = DT_INST_REG_ADDR(0),
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};
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DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, &reset_rts5817_config, PRE_KERNEL_1,
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CONFIG_RESET_INIT_PRIORITY, &reset_rts5817_driver_api);

‎drivers/reset/reset_rts5817.h

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/*
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* Copyright (c) 2024 Realtek Semiconductor, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_RESET_RESET_RTS5817_REG_H_
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#define ZEPHYR_DRIVERS_RESET_RESET_RTS5817_REG_H_
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#define SYSRST_BASE_ADDR 0x0
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#define R_SYS_FORCE_RST (SYSRST_BASE_ADDR + 0X0000)
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/* Bits of R_SYS_FORCE_RST (0X0200) */
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#define SYS_FORCE_RESET_BUS_OFFSET 0
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#define SYS_FORCE_RESET_BUS_BITS 1
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#define SYS_FORCE_RESET_BUS_MASK (((1 << 1) - 1) << 0)
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#define SYS_FORCE_RESET_BUS (SYS_FORCE_RESET_BUS_MASK)
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#define SYS_FORCE_RESET_AES_OFFSET 1
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#define SYS_FORCE_RESET_AES_BITS 1
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#define SYS_FORCE_RESET_AES_MASK (((1 << 1) - 1) << 1)
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#define SYS_FORCE_RESET_AES (SYS_FORCE_RESET_AES_MASK)
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#define SYS_FORCE_RESET_GE_OFFSET 2
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#define SYS_FORCE_RESET_GE_BITS 1
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#define SYS_FORCE_RESET_GE_MASK (((1 << 1) - 1) << 2)
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#define SYS_FORCE_RESET_GE (SYS_FORCE_RESET_GE_MASK)
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#define SYS_FORCE_RESET_SHA_OFFSET 3
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#define SYS_FORCE_RESET_SHA_BITS 1
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#define SYS_FORCE_RESET_SHA_MASK (((1 << 1) - 1) << 3)
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#define SYS_FORCE_RESET_SHA (SYS_FORCE_RESET_SHA_MASK)
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#define SYS_FORCE_RESET_SPI_CACHE_OFFSET 4
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#define SYS_FORCE_RESET_SPI_CACHE_BITS 1
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#define SYS_FORCE_RESET_SPI_CACHE_MASK (((1 << 1) - 1) << 4)
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#define SYS_FORCE_RESET_SPI_CACHE (SYS_FORCE_RESET_SPI_CACHE_MASK)
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#define SYS_FORCE_RESET_SPI_SENSOR_OFFSET 5
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#define SYS_FORCE_RESET_SPI_SENSOR_BITS 1
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#define SYS_FORCE_RESET_SPI_SENSOR_MASK (((1 << 1) - 1) << 5)
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#define SYS_FORCE_RESET_SPI_SENSOR (SYS_FORCE_RESET_SPI_SENSOR_MASK)
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#define SYS_FORCE_RESET_SPI_SSI_M_OFFSET 6
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#define SYS_FORCE_RESET_SPI_SSI_M_BITS 1
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#define SYS_FORCE_RESET_SPI_SSI_M_MASK (((1 << 1) - 1) << 6)
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#define SYS_FORCE_RESET_SPI_SSI_M (SYS_FORCE_RESET_SPI_SSI_M_MASK)
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#define SYS_FORCE_RESET_SPI_SSI_S_OFFSET 7
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#define SYS_FORCE_RESET_SPI_SSI_S_BITS 1
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#define SYS_FORCE_RESET_SPI_SSI_S_MASK (((1 << 1) - 1) << 7)
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#define SYS_FORCE_RESET_SPI_SSI_S (SYS_FORCE_RESET_SPI_SSI_S_MASK)
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#define SYS_FORCE_RESET_PKE_OFFSET 8
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#define SYS_FORCE_RESET_PKE_BITS 1
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#define SYS_FORCE_RESET_PKE_MASK (((1 << 1) - 1) << 8)
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#define SYS_FORCE_RESET_PKE (SYS_FORCE_RESET_PKE_MASK)
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#define SYS_FORCE_RESET_I2C_OFFSET 9
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#define SYS_FORCE_RESET_I2C_BITS 1
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#define SYS_FORCE_RESET_I2C_MASK (((1 << 1) - 1) << 9)
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#define SYS_FORCE_RESET_I2C (SYS_FORCE_RESET_I2C_MASK)
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#define SYS_FORCE_RESET_I2C0_OFFSET 10
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#define SYS_FORCE_RESET_I2C0_BITS 1
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#define SYS_FORCE_RESET_I2C0_MASK (((1 << 1) - 1) << 10)
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#define SYS_FORCE_RESET_I2C0 (SYS_FORCE_RESET_I2C0_MASK)
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#define SYS_FORCE_RESET_I2C1_OFFSET 11
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#define SYS_FORCE_RESET_I2C1_BITS 1
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#define SYS_FORCE_RESET_I2C1_MASK (((1 << 1) - 1) << 11)
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#define SYS_FORCE_RESET_I2C1 (SYS_FORCE_RESET_I2C1_MASK)
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#define SYS_FORCE_RESET_TRNG_OFFSET 12
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#define SYS_FORCE_RESET_TRNG_BITS 1
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#define SYS_FORCE_RESET_TRNG_MASK (((1 << 1) - 1) << 12)
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#define SYS_FORCE_RESET_TRNG (SYS_FORCE_RESET_TRNG_MASK)
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#define SYS_FORCE_RESET_I2C_S_OFFSET 13
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#define SYS_FORCE_RESET_I2C_S_BITS 1
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#define SYS_FORCE_RESET_I2C_S_MASK (((1 << 1) - 1) << 13)
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#define SYS_FORCE_RESET_I2C_S (SYS_FORCE_RESET_I2C_S_MASK)
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#define SYS_FORCE_RESET_UART0_OFFSET 14
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#define SYS_FORCE_RESET_UART0_BITS 1
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#define SYS_FORCE_RESET_UART0_MASK (((1 << 1) - 1) << 14)
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#define SYS_FORCE_RESET_UART0 (SYS_FORCE_RESET_UART0_MASK)
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#define SYS_FORCE_RESET_UART1_OFFSET 15
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#define SYS_FORCE_RESET_UART1_BITS 1
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#define SYS_FORCE_RESET_UART1_MASK (((1 << 1) - 1) << 15)
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#define SYS_FORCE_RESET_UART1 (SYS_FORCE_RESET_UART1_MASK)
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#define SYS_FORCE_RESET_PUF_OFFSET 16
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#define SYS_FORCE_RESET_PUF_BITS 1
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#define SYS_FORCE_RESET_PUF_MASK (((1 << 1) - 1) << 16)
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#define SYS_FORCE_RESET_PUF (SYS_FORCE_RESET_PUF_MASK)
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#define SYS_FORCE_RESET_USB2_OFFSET 17
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#define SYS_FORCE_RESET_USB2_BITS 1
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#define SYS_FORCE_RESET_USB2_MASK (((1 << 1) - 1) << 17)
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#define SYS_FORCE_RESET_USB2 (SYS_FORCE_RESET_USB2_MASK)
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#define SYS_FORCE_RESET_CK30M_OFFSET 18
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#define SYS_FORCE_RESET_CK30M_BITS 1
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#define SYS_FORCE_RESET_CK30M_MASK (((1 << 1) - 1) << 18)
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#define SYS_FORCE_RESET_CK30M (SYS_FORCE_RESET_CK30M_MASK)
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#define SYS_FORCE_RESET_CK60M_OFFSET 19
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#define SYS_FORCE_RESET_CK60M_BITS 1
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#define SYS_FORCE_RESET_CK60M_MASK (((1 << 1) - 1) << 19)
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#define SYS_FORCE_RESET_CK60M (SYS_FORCE_RESET_CK60M_MASK)
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#define SYS_FORCE_RESET_CK120M_OFFSET 20
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#define SYS_FORCE_RESET_CK120M_BITS 1
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#define SYS_FORCE_RESET_CK120M_MASK (((1 << 1) - 1) << 20)
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#define SYS_FORCE_RESET_CK120M (SYS_FORCE_RESET_CK120M_MASK)
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#define USB2_PHY_FORCE_RESET_OFFSET 21
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#define USB2_PHY_FORCE_RESET_BITS 1
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#define USB2_PHY_FORCE_RESET_MASK (((1 << 1) - 1) << 21)
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#define USB2_PHY_FORCE_RESET (USB2_PHY_FORCE_RESET_MASK)
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#define SYS_FORCE_RESET_SYS_OFFSET 22
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#define SYS_FORCE_RESET_SYS_BITS 1
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#define SYS_FORCE_RESET_SYS_MASK (((1 << 1) - 1) << 22)
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#define SYS_FORCE_RESET_SYS (SYS_FORCE_RESET_SYS_MASK)
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#define SYS_FORCE_RESET_DPHY_OFFSET 23
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#define SYS_FORCE_RESET_DPHY_BITS 1
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#define SYS_FORCE_RESET_DPHY_MASK (((1 << 1) - 1) << 23)
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#define SYS_FORCE_RESET_DPHY (SYS_FORCE_RESET_DPHY_MASK)
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#define SYS_FORCE_RESET_SPI_SSISLV_BUS_OFFSET 24
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#define SYS_FORCE_RESET_SPI_SSISLV_BUS_BITS 1
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#define SYS_FORCE_RESET_SPI_SSISLV_BUS_MASK (((1 << 1) - 1) << 24)
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#define SYS_FORCE_RESET_SPI_SSISLV_BUS (SYS_FORCE_RESET_SPI_SSISLV_BUS_MASK)
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#endif /* ZEPHYR_DRIVERS_RESET_RESET_RTS5817_REG_H_ */

‎dts/arm/realtek/fingerprint/rts5817/rts5817_base.dtsi

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#clock-cells = <1>;
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status = "disabled";
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};
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reset: reset@40100200 {
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compatible = "realtek,rts5817-reset";
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reg = <0x40100200 0x100>;
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#reset-cells = <1>;
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status = "disabled";
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};
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};
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};
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‎dts/bindings/reset/realtek,rts5817-reset.yaml

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# Copyright (c) 2024 Realtek Semiconductor, Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: Realtek RTS5817 Peripheral reset controller
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compatible: "realtek,rts5817-reset"
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include: [reset-controller.yaml, base.yaml]
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properties:
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"#reset-cells":
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const: 1
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reset-cells:
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- id

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