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VynDragonVynDragon
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drivers: pinctrl: Update bflb pinctrl driver
Update driver file for SDK-independance Signed-off-by: Camille BAUD <mail@massdriver.space>
1 parent 57e4ea5 commit 03107f1

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4 files changed

+138
-24
lines changed

4 files changed

+138
-24
lines changed

‎drivers/pinctrl/CMakeLists.txt

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_MPS2 pinctrl_arm_mps2.c)
1010
zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_MPS3 pinctrl_arm_mps3.c)
1111
zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_MPS4 pinctrl_arm_mps4.c)
1212
zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_V2M_BEETLE pinctrl_arm_v2m_beetle.c)
13-
zephyr_library_sources_ifdef(CONFIG_PINCTRL_BFLB pinctrl_bflb.c)
1413
zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
1514
zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
1615
zephyr_library_sources_ifdef(CONFIG_PINCTRL_ITE_IT8XXX2 pinctrl_ite_it8xxx2.c)
@@ -58,3 +57,8 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_20X_30X_AFIO pinctrl_wch_20x_30x
5857
zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_00X_AFIO pinctrl_wch_00x_afio.c)
5958

6059
add_subdirectory(renesas)
60+
61+
if (CONFIG_PINCTRL_BFLB)
62+
zephyr_library_sources(pinctrl_bflb.c)
63+
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_BL60X pinctrl_bflb_bl60x_70x.c)
64+
endif()

‎drivers/pinctrl/pinctrl_bflb.c

Lines changed: 18 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -6,40 +6,35 @@
66

77
#include <zephyr/kernel.h>
88
#include <zephyr/drivers/pinctrl.h>
9-
#include <bflb_pinctrl.h>
10-
#include <bflb_glb.h>
11-
#include <bflb_gpio.h>
129

13-
/* clang-format off */
10+
#include <zephyr/dt-bindings/pinctrl/bflb-common-pinctrl.h>
1411

15-
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
16-
uintptr_t reg)
12+
#if defined(CONFIG_SOC_SERIES_BL60X)
13+
#include <zephyr/dt-bindings/pinctrl/bl60x-pinctrl.h>
14+
#else
15+
#error "Unsupported Platform"
16+
#endif
17+
18+
void pinctrl_bflb_configure_uart(uint8_t pin, uint8_t func);
19+
void pinctrl_bflb_init_pin(pinctrl_soc_pin_t pin);
20+
21+
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
1722
{
18-
GLB_GPIO_Cfg_Type pincfg;
1923
uint8_t i;
2024

2125
ARG_UNUSED(reg);
2226

2327
for (i = 0U; i < pin_cnt; i++) {
24-
pincfg.gpioFun = BFLB_PINMUX_GET_FUN(pins[i]);
25-
pincfg.gpioMode = BFLB_PINMUX_GET_MODE(pins[i]);
26-
pincfg.gpioPin = BFLB_PINMUX_GET_PIN(pins[i]);
27-
pincfg.pullType = BFLB_PINMUX_GET_PULL_MODES(pins[i]);
28-
pincfg.smtCtrl = BFLB_PINMUX_GET_SMT(pins[i]);
29-
pincfg.drive = BFLB_PINMUX_GET_DRIVER_STRENGTH(pins[i]);
30-
31-
if (pincfg.gpioFun == BFLB_PINMUX_FUN_INST_uart0) {
32-
GLB_UART_Fun_Sel(pincfg.gpioPin % 8,
33-
(BFLB_PINMUX_GET_INST(pins[i]))
34-
* 0x4U /* rts, cts, rx, tx */
35-
+ BFLB_PINMUX_GET_SIGNAL(pins[i])
36-
);
28+
29+
if ((BFLB_PINMUX_GET_FUN(pins[i]) & BFLB_PINMUX_FUN_MASK)
30+
== BFLB_PINMUX_FUN_INST_uart0) {
31+
pinctrl_bflb_configure_uart(BFLB_PINMUX_GET_PIN(pins[i]),
32+
BFLB_PINMUX_GET_SIGNAL(pins[i]) + 4 * BFLB_PINMUX_GET_INST(pins[i]));
3733
}
3834

39-
GLB_GPIO_Init(&pincfg);
35+
/* gpio init*/
36+
pinctrl_bflb_init_pin(pins[i]);
4037
}
4138

4239
return 0;
4340
}
44-
45-
/* clang-format on */

‎drivers/pinctrl/pinctrl_bflb_bl60x_70x.c

Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,114 @@
1+
/*
2+
* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <zephyr/kernel.h>
8+
#include <zephyr/drivers/pinctrl.h>
9+
10+
#include <bflb_soc.h>
11+
#include <glb_reg.h>
12+
#include <zephyr/dt-bindings/pinctrl/bflb-common-pinctrl.h>
13+
14+
#if defined(CONFIG_SOC_SERIES_BL60X)
15+
#include <zephyr/dt-bindings/pinctrl/bl60x-pinctrl.h>
16+
#else
17+
#error "Unsupported Platform"
18+
#endif
19+
20+
void pinctrl_bflb_configure_uart(uint8_t pin, uint8_t func)
21+
{
22+
/* uart func for BL602 and BL702 Only*/
23+
uint32_t regval;
24+
uint8_t sig;
25+
uint8_t sig_pos;
26+
27+
regval = sys_read32(GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
28+
29+
sig = pin % 8;
30+
sig_pos = sig << 2;
31+
32+
regval &= (~(0x0f << sig_pos));
33+
regval |= (func << sig_pos);
34+
35+
for (uint8_t i = 0; i < 8; i++) {
36+
/* reset other sigs which are the same with uart_func */
37+
sig_pos = i << 2;
38+
if (((regval & (0x0f << sig_pos)) == (func << sig_pos)) && (i != sig) && (func !=
39+
0x0f)) {
40+
regval &= (~(0x0f << sig_pos));
41+
regval |= (0x0f << sig_pos);
42+
}
43+
}
44+
45+
sys_write32(regval, GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
46+
}
47+
48+
void pinctrl_bflb_init_pin(pinctrl_soc_pin_t pin)
49+
{
50+
uint8_t drive;
51+
uint8_t function;
52+
uint16_t mode;
53+
uint32_t regval;
54+
uint8_t real_pin;
55+
uint8_t is_odd = 0;
56+
uint32_t cfg = 0;
57+
uint32_t cfg_address;
58+
59+
real_pin = BFLB_PINMUX_GET_PIN(pin);
60+
function = BFLB_PINMUX_GET_FUN(pin);
61+
mode = BFLB_PINMUX_GET_MODE(pin);
62+
drive = BFLB_PINMUX_GET_DRIVER_STRENGTH(pin);
63+
64+
/* Disable output anyway */
65+
regval = sys_read32(GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2));
66+
regval &= ~(1 << (real_pin & 0x1f));
67+
sys_write32(regval, GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2));
68+
69+
is_odd = real_pin & 1;
70+
71+
cfg_address = GLB_BASE + GLB_GPIO_CFGCTL0_OFFSET + (real_pin / 2 * 4);
72+
cfg = sys_read32(cfg_address);
73+
cfg &= ~(0xffff << (16 * is_odd));
74+
75+
regval = sys_read32(GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2));
76+
77+
if (mode == BFLB_PINMUX_MODE_analog) {
78+
regval &= ~(1 << (real_pin & 0x1f));
79+
function = 10;
80+
} else if (mode == BFLB_PINMUX_MODE_periph) {
81+
cfg |= (1 << (is_odd * 16 + 0));
82+
regval &= ~(1 << (real_pin & 0x1f));
83+
} else {
84+
function = 11;
85+
86+
if (mode == BFLB_PINMUX_MODE_input) {
87+
cfg |= (1 << (is_odd * 16 + 0));
88+
}
89+
90+
if (mode == BFLB_PINMUX_MODE_output) {
91+
regval |= (1 << (real_pin & 0x1f));
92+
}
93+
}
94+
95+
sys_write32(regval, GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2));
96+
97+
uint8_t pull_up = BFLB_PINMUX_GET_PULL_UP(pin);
98+
uint8_t pull_down = BFLB_PINMUX_GET_PULL_DOWN(pin);
99+
100+
if (pull_up) {
101+
cfg |= (1 << (is_odd * 16 + 4));
102+
} else if (pull_down) {
103+
cfg |= (1 << (is_odd * 16 + 5));
104+
} else {
105+
}
106+
107+
if (BFLB_PINMUX_GET_SMT(pin)) {
108+
cfg |= (1 << (is_odd * 16 + 1));
109+
}
110+
111+
cfg |= (drive << (is_odd * 16 + 2));
112+
cfg |= (function << (is_odd * 16 + 8));
113+
sys_write32(cfg, cfg_address);
114+
}

‎include/zephyr/drivers/pinctrl/pinctrl_soc_bflb_common.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414

1515
#include <zephyr/devicetree.h>
1616
#include <zephyr/types.h>
17+
#include <zephyr/dt-bindings/pinctrl/bflb-common-pinctrl.h>
1718

1819
/* clang-format off */
1920

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