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drivers/watchdog/it51xxx: implement watchdog driver
Implement watchdog driver for ITE it51xxx series chip. Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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‎boards/ite/it515xx_evb/it515xx_evb.dts

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@@ -16,6 +16,7 @@
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aliases {
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led0 = &led0;
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watchdog0 = &twd0;
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};
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chosen {

‎drivers/watchdog/CMakeLists.txt

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@@ -17,6 +17,7 @@ zephyr_library_sources_ifdef(CONFIG_WDT_CC13XX_CC26XX wdt_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_ESP32 wdt_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_XT_ESP32 xt_wdt_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_GECKO wdt_gecko.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_ITE_IT51XXX wdt_ite_it51xxx.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_ITE_IT8XXX2 wdt_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_LITEX wdt_litex.c)
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zephyr_library_sources_ifdef(CONFIG_WDT_MAX32 wdt_max32.c)

‎drivers/watchdog/Kconfig

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@@ -97,6 +97,8 @@ source "drivers/watchdog/Kconfig.cc32xx"
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source "drivers/watchdog/Kconfig.cc13xx_cc26xx"
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source "drivers/watchdog/Kconfig.it51xxx"
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source "drivers/watchdog/Kconfig.it8xxx2"
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source "drivers/watchdog/Kconfig.rpi_pico"

‎drivers/watchdog/Kconfig.it51xxx

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# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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config WDT_ITE_IT51XXX
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bool "ITE it51xxx Watchdog Timer (WDT) driver"
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default y
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depends on DT_HAS_ITE_IT51XXX_WATCHDOG_ENABLED
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select HAS_WDT_DISABLE_AT_BOOT
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help
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This option enables the Watchdog Timer driver for ITE it51xxx.
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This driver supports only one channel that id is 0 and 16-bits
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resolution WDT.
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config WDT_ITE_WARNING_LEADING_TIME_MS
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int "Number of ms before generating watchdog event/signal"
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depends on WDT_ITE_IT51XXX
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default 500
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help
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This option defines the window in which a watchdog event must be
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handled. After this time window, the watchdog reset triggers
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immediately.
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config WDT_ITE_REDUCE_WARNING_LEADING_TIME
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bool "Reduce warning leading time"
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depends on WDT_ITE_IT51XXX
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help
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Once warning timer triggered, if watchdog timer isn't reloaded,
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then we will reduce interval of warning timer to 30ms to print
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more warning messages before watchdog reset.

‎drivers/watchdog/wdt_ite_it51xxx.c

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/*
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* Copyright (c) 2025 ITE Corporation. All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_it51xxx_watchdog
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#include <errno.h>
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#include <soc.h>
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#include <zephyr/drivers/watchdog.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
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LOG_MODULE_REGISTER(wdt_ite_it51xxx);
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#define IT51XXX_WATCHDOG_MAGIC_BYTE 0x5c
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#define WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(ms) ((ms) * 1024 / 1000)
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/* 0x81: External Timer1/WDT Configuration */
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#define REG_ETWCFG 0x01
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#define WDT_EWDKEYEN BIT(5)
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#define WDT_EWDSRC BIT(4)
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#define WDT_LEWDCNTL BIT(3)
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#define WDT_LET1CNTL BIT(2)
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#define WDT_LET1PS BIT(1)
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#define WDT_LETWCFG BIT(0)
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/* 0x82: External Timer1 Prescaler */
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#define REG_ET1PSR 0x02
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#define WDT_ETPS_32P768_KHZ 0x00
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#define WDT_ETPS_1P024_KHZ 0x01
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#define WDT_ETPS_32_HZ 0x02
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/* 0x83: External Timer1 Counter High Byte */
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#define REG_ET1CNTLHR 0x03
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/* 0x84: External Timer1 Counter Low Byte */
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#define REG_ET1CNTLLR 0x04
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/* 0x85: External Timer1/WDT Control */
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#define REG_ETWCTRL 0x05
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#define WDT_EWDSCEN BIT(5)
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#define WDT_EWDSCMS BIT(4)
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#define WDT_ET1TC BIT(1)
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#define WDT_ET1RST BIT(0)
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/* 0x86: External WDT Counter Low Byte */
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#define REG_EWDCNTLR 0x06
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/* 0x87: External WDT Key */
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#define REG_EWDKEYR 0x07
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/* 0x89: External WDT Counter High Byte */
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#define REG_EWDCNTHR 0x09
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/* device config */
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struct wdt_it51xxx_config {
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/* wdt register base address */
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uintptr_t base;
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};
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/* driver data */
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struct wdt_it51xxx_data {
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/* timeout callback used to handle watchdog event */
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wdt_callback_t callback;
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/* indicate whether a watchdog timeout is installed */
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bool timeout_installed;
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/* watchdog feed timeout in milliseconds */
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uint32_t timeout;
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/* pre-warning timer1 fired times */
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int wdt_warning_fired;
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};
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static int wdt_it51xxx_install_timeout(const struct device *dev,
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const struct wdt_timeout_cfg *config)
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{
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const struct wdt_it51xxx_config *const wdt_config = dev->config;
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struct wdt_it51xxx_data *data = dev->data;
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const uintptr_t base = wdt_config->base;
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/* if watchdog is already running */
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if (sys_read8(base + REG_ETWCFG) & WDT_LEWDCNTL) {
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return -EBUSY;
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}
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/*
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* Not support lower limit window timeouts (min value must be equal to
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* 0). Upper limit window timeouts can't be 0 when we install timeout.
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*/
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if ((config->window.min != 0) || (config->window.max == 0)) {
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data->timeout_installed = false;
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return -EINVAL;
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}
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/* save watchdog timeout */
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data->timeout = config->window.max;
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/* install user timeout isr */
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data->callback = config->callback;
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/* mark installed */
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data->timeout_installed = true;
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return 0;
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}
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static int wdt_it51xxx_setup(const struct device *dev, uint8_t options)
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{
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const struct wdt_it51xxx_config *const wdt_config = dev->config;
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struct wdt_it51xxx_data *data = dev->data;
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const uintptr_t base = wdt_config->base;
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uint16_t cnt0 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(data->timeout);
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uint16_t cnt1 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(
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(data->timeout + CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS));
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uint8_t reg_val;
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/* disable pre-warning timer1 interrupt */
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irq_disable(DT_INST_IRQN(0));
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if (!data->timeout_installed) {
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LOG_ERR("No valid WDT timeout installed");
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return -EINVAL;
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}
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if (sys_read8(base + REG_ETWCFG) & WDT_LEWDCNTL) {
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LOG_ERR("WDT is already running");
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return -EBUSY;
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}
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if ((options & WDT_OPT_PAUSE_IN_SLEEP) != 0) {
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LOG_ERR("WDT_OPT_PAUSE_IN_SLEEP is not supported");
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return -ENOTSUP;
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}
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/* pre-warning timer1 is 16-bit counter down timer */
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sys_write8((cnt0 >> 8) & 0xff, base + REG_ET1CNTLHR);
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sys_write8(cnt0 & 0xff, base + REG_ET1CNTLLR);
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/* clear pre-warning timer1 interrupt status */
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ite_intc_isr_clear(DT_INST_IRQN(0));
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/* enable pre-warning timer1 interrupt */
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irq_enable(DT_INST_IRQN(0));
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/* don't stop watchdog timer counting */
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reg_val = sys_read8(base + REG_ETWCTRL);
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sys_write8(reg_val & ~WDT_EWDSCEN, base + REG_ETWCTRL);
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/* set watchdog timer count */
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sys_write8((cnt1 >> 8) & 0xff, base + REG_EWDCNTHR);
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sys_write8(cnt1 & 0xff, base + REG_EWDCNTLR);
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/* allow to write timer1 count register */
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reg_val = sys_read8(base + REG_ETWCFG);
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sys_write8(reg_val & ~WDT_LET1CNTL, base + REG_ETWCFG);
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/*
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* bit5 = 1: enable key match function to touch watchdog
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* bit4 = 1: select watchdog clock source from prescaler
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* bit3 = 1: lock watchdog count register (also mark as watchdog running)
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* bit1 = 1: lock timer1 prescaler register
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*/
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sys_write8((WDT_EWDKEYEN | WDT_EWDSRC | WDT_LEWDCNTL | WDT_LET1PS), base + REG_ETWCFG);
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LOG_DBG("WDT Setup and enabled");
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return 0;
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}
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/*
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* reload the WDT and pre-warning timer1 counter
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*
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* @param dev Pointer to the device structure for the driver instance.
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* @param channel_id Index of the fed channel, and we only support
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* channel_id = 0 now.
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*/
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static int wdt_it51xxx_feed(const struct device *dev, int channel_id)
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{
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const struct wdt_it51xxx_config *const wdt_config = dev->config;
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struct wdt_it51xxx_data *data = dev->data;
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const uintptr_t base = wdt_config->base;
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uint16_t cnt0 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(data->timeout);
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uint8_t reg_val;
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ARG_UNUSED(channel_id);
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/* reset pre-warning timer1 */
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reg_val = sys_read8(base + REG_ETWCTRL);
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sys_write8(reg_val | WDT_ET1RST, base + REG_ETWCTRL);
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/* restart watchdog timer */
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sys_write8(IT51XXX_WATCHDOG_MAGIC_BYTE, base + REG_EWDKEYR);
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/* reset pre-warning timer1 to default if time is touched */
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if (data->wdt_warning_fired) {
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data->wdt_warning_fired = 0;
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/* pre-warning timer1 is 16-bit counter down timer */
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sys_write8((cnt0 >> 8) & 0xff, base + REG_ET1CNTLHR);
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sys_write8(cnt0 & 0xff, base + REG_ET1CNTLLR);
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/* clear timer1 interrupt status */
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ite_intc_isr_clear(DT_INST_IRQN(0));
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/* enable timer1 interrupt */
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irq_enable(DT_INST_IRQN(0));
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}
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LOG_DBG("WDT Kicking");
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return 0;
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}
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static int wdt_it51xxx_disable(const struct device *dev)
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{
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const struct wdt_it51xxx_config *const wdt_config = dev->config;
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struct wdt_it51xxx_data *data = dev->data;
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const uintptr_t base = wdt_config->base;
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uint8_t reg_val;
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/* stop watchdog timer counting */
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reg_val = sys_read8(base + REG_ETWCTRL);
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sys_write8(reg_val | WDT_EWDSCEN, base + REG_ETWCTRL);
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/* unlock watchdog count register (also mark as watchdog not running) */
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reg_val = sys_read8(base + REG_ETWCFG);
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sys_write8(reg_val & ~WDT_LEWDCNTL, base + REG_ETWCFG);
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/* disable pre-warning timer1 interrupt */
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irq_disable(DT_INST_IRQN(0));
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/* mark uninstalled */
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data->timeout_installed = false;
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LOG_DBG("WDT Disabled");
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return 0;
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}
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static void wdt_it51xxx_isr(const struct device *dev)
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{
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const struct wdt_it51xxx_config *const wdt_config = dev->config;
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struct wdt_it51xxx_data *data = dev->data;
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const uintptr_t base = wdt_config->base;
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uint8_t reg_val;
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/* clear pre-warning timer1 interrupt status */
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ite_intc_isr_clear(DT_INST_IRQN(0));
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/* reset pre-warning timer1 */
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reg_val = sys_read8(base + REG_ETWCTRL);
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sys_write8(reg_val | WDT_ET1RST, base + REG_ETWCTRL);
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/* callback function, ex. print warning message */
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if (data->callback) {
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data->callback(dev, 0);
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}
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if (IS_ENABLED(CONFIG_WDT_ITE_REDUCE_WARNING_LEADING_TIME)) {
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/*
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* Once warning timer triggered: if watchdog timer isn't reloaded,
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* then we will reduce interval of warning timer to 30ms to print
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* more warning messages before watchdog reset.
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*/
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if (!(data->wdt_warning_fired)) {
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uint16_t cnt0 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(30);
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/* pre-warning timer1 is 16-bit counter down timer */
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sys_write8((cnt0 >> 8) & 0xff, base + REG_ET1CNTLHR);
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sys_write8(cnt0 & 0xff, base + REG_ET1CNTLLR);
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/* clear pre-warning timer1 interrupt status */
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ite_intc_isr_clear(DT_INST_IRQN(0));
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}
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}
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data->wdt_warning_fired++;
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LOG_DBG("WDT ISR");
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}
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static DEVICE_API(wdt, wdt_it51xxx_api) = {
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.setup = wdt_it51xxx_setup,
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.disable = wdt_it51xxx_disable,
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.install_timeout = wdt_it51xxx_install_timeout,
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.feed = wdt_it51xxx_feed,
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};
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static int wdt_it51xxx_init(const struct device *dev)
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{
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const struct wdt_it51xxx_config *const wdt_config = dev->config;
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const uintptr_t base = wdt_config->base;
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uint8_t reg_val;
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if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
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wdt_it51xxx_disable(dev);
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}
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/* unlock access to watchdog registers */
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sys_write8(0x00, base + REG_ETWCFG);
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/* set WDT and timer1 to use 1.024kHz clock */
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sys_write8(WDT_ETPS_1P024_KHZ, base + REG_ET1PSR);
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/* set WDT key match enabled and WDT clock to use ET1PSR */
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sys_write8(WDT_EWDKEYEN | WDT_EWDSRC, base + REG_ETWCFG);
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/*
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* select the mode that watchdog can be stopped, this is needed for
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* wdt_it51xxx_disable() api and WDT_OPT_PAUSE_HALTED_BY_DBG flag
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*/
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reg_val = sys_read8(base + REG_ETWCTRL);
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sys_write8(reg_val | WDT_EWDSCMS, base + REG_ETWCTRL);
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IRQ_CONNECT(DT_INST_IRQN(0), 0, wdt_it51xxx_isr, DEVICE_DT_INST_GET(0), 0);
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return 0;
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}
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static const struct wdt_it51xxx_config wdt_it51xxx_cfg_0 = {
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.base = DT_INST_REG_ADDR(0),
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};
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static struct wdt_it51xxx_data wdt_it51xxx_dev_data;
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DEVICE_DT_INST_DEFINE(0, wdt_it51xxx_init, NULL, &wdt_it51xxx_dev_data, &wdt_it51xxx_cfg_0,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &wdt_it51xxx_api);
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
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"only one ite,it51xxx-watchdog compatible node can be supported");

‎dts/bindings/watchdog/ite,it51xxx-watchdog.yaml

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# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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description: ITE watchdog timer
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include: base.yaml
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compatible: "ite,it51xxx-watchdog"
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properties:
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reg:
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required: true
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interrupts:
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required: true

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