drivers: flash: spi_nor: Add fast read support

Most SPI NOR flash devices support a "fast read" command which uses
dummy bits between the address and the start of the data transfer. In
many cases, the maximum SPI clock speed of the device is lower for the
regular read command due to the limited time between the address and
data phases, so using the fast read command will remove this restriction
and allow for faster transfers.

Add a device tree flag to indicate that fast reads should be used for
the device.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>

Author: robhancocksed

drivers/flash/spi_nor.c

@@ -55,6 +55,7 @@ LOG_MODULE_REGISTER(spi_nor, CONFIG_FLASH_LOG_LEVEL);
 #define ANY_INST_USE_4B_ADDR_OPCODES DT_ANY_INST_HAS_BOOL_STATUS_OKAY(use_4b_addr_opcodes)
 #define ANY_INST_HAS_FLSR \
 	DT_ANY_INST_HAS_BOOL_STATUS_OKAY(use_flag_status_register)
+#define ANY_INST_USE_FAST_READ DT_ANY_INST_HAS_BOOL_STATUS_OKAY(use_fast_read)
 
 #ifdef CONFIG_SPI_NOR_ACTIVE_DWELL_MS
 #define ACTIVE_DWELL_MS CONFIG_SPI_NOR_ACTIVE_DWELL_MS
@@ -153,6 +154,7 @@ struct spi_nor_config {
 	bool wp_gpios_exist:1;
 	bool hold_gpios_exist:1;
 	bool has_flsr: 1;
+	bool use_fast_read: 1;
 };
 
 /**
@@ -359,6 +361,10 @@ static inline void delay_until_exit_dpd_ok(const struct device *const dev)
  */
 #define NOR_ACCESS_32BIT_ADDR BIT(2)
 
+/* Indicates that a dummy byte is to be sent following the address.
+ */
+#define NOR_ACCESS_DUMMY_BYTE BIT(3)
+
 /* Indicates that an access command is performing a write.  If not
  * provided access is a read.
  */
@@ -384,7 +390,8 @@ static int spi_nor_access(const struct device *const dev,
 	struct spi_nor_data *const driver_data = dev->data;
 	bool is_addressed = (access & NOR_ACCESS_ADDRESSED) != 0U;
 	bool is_write = (access & NOR_ACCESS_WRITE) != 0U;
-	uint8_t buf[5] = {opcode};
+	bool has_dummy = (access & NOR_ACCESS_DUMMY_BYTE) != 0U;
+	uint8_t buf[6] = {opcode};
 	struct spi_buf spi_buf_tx[2] = {
 		{
 			.buf = buf,
@@ -429,6 +436,10 @@ static int spi_nor_access(const struct device *const dev,
 			spi_buf_rx[0].len += 3;
 		}
 	};
+	if (has_dummy) {
+		spi_buf_tx[0].len++;
+		spi_buf_rx[0].len++;
+	}
 
 	const struct spi_buf_set tx_set = {
 		.buffers = spi_buf_tx,
@@ -457,6 +468,17 @@ static int spi_nor_access(const struct device *const dev,
 #define spi_nor_cmd_addr_read_4b(dev, opcode, addr, dest, length)                                  \
 	spi_nor_access(dev, opcode, NOR_ACCESS_32BIT_ADDR | NOR_ACCESS_ADDRESSED, addr, dest,      \
 		       length)
+#define spi_nor_cmd_addr_fast_read(dev, opcode, addr, dest, length)                                \
+	spi_nor_access(dev, opcode, NOR_ACCESS_ADDRESSED | NOR_ACCESS_DUMMY_BYTE, addr, dest,      \
+		       length)
+#define spi_nor_cmd_addr_fast_read_3b(dev, opcode, addr, dest, length)                             \
+	spi_nor_access(dev, opcode,                                                                \
+		       NOR_ACCESS_24BIT_ADDR | NOR_ACCESS_ADDRESSED | NOR_ACCESS_DUMMY_BYTE, addr, \
+		       dest, length)
+#define spi_nor_cmd_addr_fast_read_4b(dev, opcode, addr, dest, length)                             \
+	spi_nor_access(dev, opcode,                                                                \
+		       NOR_ACCESS_32BIT_ADDR | NOR_ACCESS_ADDRESSED | NOR_ACCESS_DUMMY_BYTE, addr, \
+		       dest, length)
 #define spi_nor_cmd_write(dev, opcode) \
 	spi_nor_access(dev, opcode, NOR_ACCESS_WRITE, 0, NULL, 0)
 #define spi_nor_cmd_addr_write(dev, opcode, addr, src, length) \
@@ -839,6 +861,7 @@ static int mxicy_configure(const struct device *dev, const uint8_t *jedec_id)
 static int spi_nor_read(const struct device *dev, off_t addr, void *dest,
 			size_t size)
 {
+	const struct spi_nor_config *cfg = dev->config;
 	const size_t flash_size = dev_flash_size(dev);
 	int ret;
 
@@ -854,14 +877,31 @@ static int spi_nor_read(const struct device *dev, off_t addr, void *dest,
 
 	acquire_device(dev);
 
-	if (IS_ENABLED(ANY_INST_USE_4B_ADDR_OPCODES) && DEV_CFG(dev)->use_4b_addr_opcodes) {
+	if (IS_ENABLED(ANY_INST_USE_4B_ADDR_OPCODES) && cfg->use_4b_addr_opcodes) {
 		if (addr > SPI_NOR_3B_ADDR_MAX) {
-			ret = spi_nor_cmd_addr_read_4b(dev, SPI_NOR_CMD_READ_4B, addr, dest, size);
+			if (IS_ENABLED(ANY_INST_USE_FAST_READ) && cfg->use_fast_read) {
+				ret = spi_nor_cmd_addr_fast_read_4b(dev, SPI_NOR_CMD_READ_FAST_4B,
+								    addr, dest, size);
+			} else {
+				ret = spi_nor_cmd_addr_read_4b(dev, SPI_NOR_CMD_READ_4B, addr, dest,
+							       size);
+			}
 		} else {
-			ret = spi_nor_cmd_addr_read_3b(dev, SPI_NOR_CMD_READ, addr, dest, size);
+			if (IS_ENABLED(ANY_INST_USE_FAST_READ) && cfg->use_fast_read) {
+				ret = spi_nor_cmd_addr_fast_read_3b(dev, SPI_NOR_CMD_READ_FAST,
+								    addr, dest, size);
+			} else {
+				ret = spi_nor_cmd_addr_read_3b(dev, SPI_NOR_CMD_READ, addr, dest,
+							       size);
+			}
 		}
 	} else {
-		ret = spi_nor_cmd_addr_read(dev, SPI_NOR_CMD_READ, addr, dest, size);
+		if (IS_ENABLED(ANY_INST_USE_FAST_READ) && cfg->use_fast_read) {
+			ret = spi_nor_cmd_addr_fast_read(dev, SPI_NOR_CMD_READ_FAST, addr, dest,
+							 size);
+		} else {
+			ret = spi_nor_cmd_addr_read(dev, SPI_NOR_CMD_READ, addr, dest, size);
+		}
 	}
 
 	release_device(dev);
@@ -1859,6 +1899,7 @@ static DEVICE_API(flash, spi_nor_api) = {
 		.hold_gpios_exist = DT_INST_NODE_HAS_PROP(idx, hold_gpios),			\
 		.use_4b_addr_opcodes = DT_INST_PROP(idx, use_4b_addr_opcodes),			\
 		.has_flsr = DT_INST_PROP(idx, use_flag_status_register),			\
+		.use_fast_read = DT_INST_PROP(idx, use_fast_read),				\
 		IF_ENABLED(INST_HAS_LOCK(idx), (.has_lock = DT_INST_PROP(idx, has_lock),))	\
 		IF_ENABLED(ANY_INST_HAS_DPD, (INIT_T_ENTER_DPD(idx),))				\
 		IF_ENABLED(UTIL_AND(ANY_INST_HAS_DPD, ANY_INST_HAS_T_EXIT_DPD),			\

dts/bindings/mtd/jedec,spi-nor-common.yaml

@@ -123,3 +123,13 @@ properties:
       which indicates more details on the status of program or erase operations.
       In some cases, program operations will not function properly if the flag
       status register is not read after the operation.
+
+  use-fast-read:
+    type: boolean
+    description: |
+      Indicates the device supports fast read.
+
+      Most SPI NOR devices support a fast read command that allows the device to
+      output data at a higher clock rate than the standard read command.  This
+      property indicates that the device supports the fast read command with
+      8 dummy cycles after the address phase of the command.