Skip to content

Commit e3dd6ac

Browse files
andyrossstephanosio
andyross
authored and
stephanosio
committed
xtensa: Add MediaTek adsp toolchains
Add toolchains for mt8186/88 and mt8196. Note that the directory layout of the overlay is slightly different from existing overlays, conforming to the files as shipped by recent (RJ-2024.3) versions of the Cadence tooling. crosstools-ng appears to support both, but this is easier to maintain. Signed-off-by: Andy Ross <andyross@google.com>
1 parent 66e5f92 commit e3dd6ac

23 files changed

+981765
-2
lines changed

‎.github/workflows/ci.yml

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,8 @@ on:
6161
- xtensa-intel_ace30_ptl_zephyr-elf
6262
- xtensa-intel_tgl_adsp_zephyr-elf
6363
- xtensa-mtk_mt8195_adsp_zephyr-elf
64+
- xtensa-mtk_mt818x_adsp_zephyr-elf
65+
- xtensa-mtk_mt8196_adsp_zephyr-elf
6466
- xtensa-nxp_imx_adsp_zephyr-elf
6567
- xtensa-nxp_imx8m_adsp_zephyr-elf
6668
- xtensa-nxp_imx8ulp_adsp_zephyr-elf
@@ -179,6 +181,8 @@ jobs:
179181
xtensa-intel_ace30_ptl_zephyr-elf) build_target_xtensa_intel_ace30_ptl_zephyr_elf="y";;
180182
xtensa-intel_tgl_adsp_zephyr-elf) build_target_xtensa_intel_tgl_adsp_zephyr_elf="y";;
181183
xtensa-mtk_mt8195_adsp_zephyr-elf) build_target_xtensa_mtk_mt8195_adsp_zephyr_elf="y";;
184+
xtensa-mtk_mt818x_adsp_zephyr-elf) build_target_xtensa_mtk_mt818x_adsp_zephyr_elf="y";;
185+
xtensa-mtk_mt8196_adsp_zephyr-elf) build_target_xtensa_mtk_mt8196_adsp_zephyr_elf="y";;
182186
xtensa-nxp_imx_adsp_zephyr-elf) build_target_xtensa_nxp_imx_adsp_zephyr_elf="y";;
183187
xtensa-nxp_imx8m_adsp_zephyr-elf) build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y";;
184188
xtensa-nxp_imx8ulp_adsp_zephyr-elf) build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf="y";;
@@ -225,6 +229,8 @@ jobs:
225229
build_target_xtensa_intel_ace30_ptl_zephyr_elf="y"
226230
build_target_xtensa_intel_tgl_adsp_zephyr_elf="y"
227231
build_target_xtensa_mtk_mt8195_adsp_zephyr_elf="y"
232+
build_target_xtensa_mtk_mt818x_adsp_zephyr_elf="y"
233+
build_target_xtensa_mtk_mt8196_adsp_zephyr_elf="y"
228234
build_target_xtensa_nxp_imx_adsp_zephyr_elf="y"
229235
build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y"
230236
build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf="y"
@@ -311,6 +317,8 @@ jobs:
311317
[ "${build_target_xtensa_intel_ace30_ptl_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_ace30_ptl_zephyr-elf",'
312318
[ "${build_target_xtensa_intel_tgl_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_tgl_adsp_zephyr-elf",'
313319
[ "${build_target_xtensa_mtk_mt8195_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-mtk_mt8195_adsp_zephyr-elf",'
320+
[ "${build_target_xtensa_mtk_mt818x_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-mtk_mt818x_adsp_zephyr-elf",'
321+
[ "${build_target_xtensa_mtk_mt8196_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-mtk_mt8196_adsp_zephyr-elf",'
314322
[ "${build_target_xtensa_nxp_imx_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx_adsp_zephyr-elf",'
315323
[ "${build_target_xtensa_nxp_imx8m_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8m_adsp_zephyr-elf",'
316324
[ "${build_target_xtensa_nxp_imx8ulp_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8ulp_adsp_zephyr-elf",'
@@ -1582,8 +1590,16 @@ jobs:
15821590
PLATFORM_ARGS+="-p intel_adsp/cavs25 "
15831591
;;
15841592
xtensa-mtk_mt8195_adsp_zephyr-elf)
1585-
# xtensa-mtk_mt8195_adsp_zephyr-elf is untested because no
1586-
# upstream user platform is currently available.
1593+
# Not merged yet, see Zephyr #81154
1594+
#PLATFORM_ARGS+="-p mt8195/mt8195/adsp"
1595+
;;
1596+
xtensa-mtk_mt818x_adsp_zephyr-elf)
1597+
# Not merged yet, see Zephyr #81154
1598+
#PLATFORM_ARGS+="-p mt818x/mt818x/adsp"
1599+
;;
1600+
xtensa-mtk_mt8196_adsp_zephyr-elf)
1601+
# Not merged yet, see Zephyr #81154
1602+
#PLATFORM_ARGS+="-p mt8196/mt8196/adsp"
15871603
;;
15881604
xtensa-nxp_imx_adsp_zephyr-elf)
15891605
PLATFORM_ARGS+="-p imx8qm_mek/mimx8qm6/adsp "

‎configs/xtensa-mtk_mt818x_adsp_zephyr-elf.config

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
CT_CONFIG_VERSION="3"
2+
CT_EXPERIMENTAL=y
3+
CT_OVERLAY_LOCATION="overlays"
4+
CT_OVERLAY_NAME="mtk_mt818x_adsp"
5+
CT_ARCH_XTENSA=y
6+
CT_XTENSA_CUSTOM=y
7+
CT_TARGET_VENDOR="mtk_mt818x_adsp_zephyr"
8+
CT_TARGET_CFLAGS="-ftls-model=local-exec"
9+
CT_CC_GCC_CONFIG_TLS=n
10+
CT_GDB_CROSS_EXTRA_CONFIG_ARRAY="--enable-xtensa-use-target-regnum --disable-xtensa-remote-g-packet"

‎configs/xtensa-mtk_mt8196_adsp_zephyr-elf.config

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
CT_CONFIG_VERSION="3"
2+
CT_EXPERIMENTAL=y
3+
CT_OVERLAY_LOCATION="overlays"
4+
CT_OVERLAY_NAME="mtk_mt8196_adsp"
5+
CT_ARCH_XTENSA=y
6+
CT_XTENSA_CUSTOM=y
7+
CT_TARGET_VENDOR="mtk_mt8196_adsp_zephyr"
8+
CT_TARGET_CFLAGS="-ftls-model=local-exec"
9+
CT_GDB_CROSS_EXTRA_CONFIG_ARRAY="--enable-xtensa-use-target-regnum --disable-xtensa-remote-g-packet"
10+
CT_CC_GCC_CONFIG_TLS=n

‎overlays/xtensa_mtk_mt818x_adsp/binutils/xtensa-config.h

Lines changed: 185 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,185 @@
1+
/* Xtensa configuration settings.
2+
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
3+
Free Software Foundation, Inc.
4+
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
5+
6+
This program is free software; you can redistribute it and/or modify
7+
it under the terms of the GNU General Public License as published by
8+
the Free Software Foundation; either version 2, or (at your option)
9+
any later version.
10+
11+
This program is distributed in the hope that it will be useful, but
12+
WITHOUT ANY WARRANTY; without even the implied warranty of
13+
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14+
General Public License for more details.
15+
16+
You should have received a copy of the GNU General Public License
17+
along with this program; if not, write to the Free Software
18+
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
19+
20+
#ifndef XTENSA_CONFIG_H
21+
#define XTENSA_CONFIG_H
22+
23+
/* The macros defined here match those with the same names in the Xtensa
24+
compile-time HAL (Hardware Abstraction Layer). Please refer to the
25+
Xtensa System Software Reference Manual for documentation of these
26+
macros. */
27+
28+
#undef XCHAL_HAVE_BE
29+
#define XCHAL_HAVE_BE 0
30+
31+
#undef XCHAL_HAVE_DENSITY
32+
#define XCHAL_HAVE_DENSITY 1
33+
34+
#undef XCHAL_HAVE_CONST16
35+
#define XCHAL_HAVE_CONST16 0
36+
37+
#undef XCHAL_HAVE_ABS
38+
#define XCHAL_HAVE_ABS 1
39+
40+
#undef XCHAL_HAVE_ADDX
41+
#define XCHAL_HAVE_ADDX 1
42+
43+
#undef XCHAL_HAVE_L32R
44+
#define XCHAL_HAVE_L32R 1
45+
46+
#undef XSHAL_USE_ABSOLUTE_LITERALS
47+
#define XSHAL_USE_ABSOLUTE_LITERALS 0
48+
49+
#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
50+
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
51+
52+
#undef XCHAL_HAVE_MAC16
53+
#define XCHAL_HAVE_MAC16 0
54+
55+
#undef XCHAL_HAVE_MUL16
56+
#define XCHAL_HAVE_MUL16 1
57+
58+
#undef XCHAL_HAVE_MUL32
59+
#define XCHAL_HAVE_MUL32 1
60+
61+
#undef XCHAL_HAVE_MUL32_HIGH
62+
#define XCHAL_HAVE_MUL32_HIGH 0
63+
64+
#undef XCHAL_HAVE_DIV32
65+
#define XCHAL_HAVE_DIV32 1
66+
67+
#undef XCHAL_HAVE_NSA
68+
#define XCHAL_HAVE_NSA 1
69+
70+
#undef XCHAL_HAVE_MINMAX
71+
#define XCHAL_HAVE_MINMAX 1
72+
73+
#undef XCHAL_HAVE_SEXT
74+
#define XCHAL_HAVE_SEXT 1
75+
76+
#undef XCHAL_HAVE_LOOPS
77+
#define XCHAL_HAVE_LOOPS 1
78+
79+
#undef XCHAL_HAVE_THREADPTR
80+
#define XCHAL_HAVE_THREADPTR 1
81+
82+
#undef XCHAL_HAVE_RELEASE_SYNC
83+
#define XCHAL_HAVE_RELEASE_SYNC 1
84+
85+
#undef XCHAL_HAVE_S32C1I
86+
#define XCHAL_HAVE_S32C1I 0
87+
88+
#undef XCHAL_HAVE_BOOLEANS
89+
#define XCHAL_HAVE_BOOLEANS 1
90+
91+
#undef XCHAL_HAVE_FP
92+
#define XCHAL_HAVE_FP 0
93+
94+
#undef XCHAL_HAVE_FP_DIV
95+
#define XCHAL_HAVE_FP_DIV 0
96+
97+
#undef XCHAL_HAVE_FP_RECIP
98+
#define XCHAL_HAVE_FP_RECIP 0
99+
100+
#undef XCHAL_HAVE_FP_SQRT
101+
#define XCHAL_HAVE_FP_SQRT 0
102+
103+
#undef XCHAL_HAVE_FP_RSQRT
104+
#define XCHAL_HAVE_FP_RSQRT 0
105+
106+
#undef XCHAL_HAVE_DFP_ACCEL
107+
#define XCHAL_HAVE_DFP_ACCEL 0
108+
/* For backward compatibility */
109+
#undef XCHAL_HAVE_DFP_accel
110+
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
111+
112+
#undef XCHAL_HAVE_WINDOWED
113+
#define XCHAL_HAVE_WINDOWED 1
114+
115+
#undef XCHAL_NUM_AREGS
116+
#define XCHAL_NUM_AREGS 64
117+
118+
#undef XCHAL_HAVE_WIDE_BRANCHES
119+
#define XCHAL_HAVE_WIDE_BRANCHES 0
120+
121+
#undef XCHAL_ICACHE_SIZE
122+
#define XCHAL_ICACHE_SIZE 65536
123+
124+
#undef XCHAL_DCACHE_SIZE
125+
#define XCHAL_DCACHE_SIZE 131072
126+
127+
#undef XCHAL_ICACHE_LINESIZE
128+
#define XCHAL_ICACHE_LINESIZE 128
129+
130+
#undef XCHAL_DCACHE_LINESIZE
131+
#define XCHAL_DCACHE_LINESIZE 128
132+
133+
#undef XCHAL_ICACHE_LINEWIDTH
134+
#define XCHAL_ICACHE_LINEWIDTH 7
135+
136+
#undef XCHAL_DCACHE_LINEWIDTH
137+
#define XCHAL_DCACHE_LINEWIDTH 7
138+
139+
#undef XCHAL_DCACHE_IS_WRITEBACK
140+
#define XCHAL_DCACHE_IS_WRITEBACK 1
141+
142+
143+
#undef XCHAL_HAVE_MMU
144+
#define XCHAL_HAVE_MMU 0
145+
146+
147+
#undef XCHAL_HAVE_DEBUG
148+
#define XCHAL_HAVE_DEBUG 1
149+
150+
#undef XCHAL_NUM_IBREAK
151+
#define XCHAL_NUM_IBREAK 2
152+
153+
#undef XCHAL_NUM_DBREAK
154+
#define XCHAL_NUM_DBREAK 2
155+
156+
#undef XCHAL_DEBUGLEVEL
157+
#define XCHAL_DEBUGLEVEL 5
158+
159+
160+
#undef XCHAL_MAX_INSTRUCTION_SIZE
161+
#define XCHAL_MAX_INSTRUCTION_SIZE 16
162+
163+
#undef XCHAL_INST_FETCH_WIDTH
164+
#define XCHAL_INST_FETCH_WIDTH 16
165+
166+
167+
#undef XSHAL_ABI
168+
#undef XTHAL_ABI_WINDOWED
169+
#undef XTHAL_ABI_CALL0
170+
#define XSHAL_ABI XTHAL_ABI_WINDOWED
171+
#define XTHAL_ABI_WINDOWED 0
172+
#define XTHAL_ABI_CALL0 1
173+
174+
175+
#undef XCHAL_M_STAGE
176+
#define XCHAL_M_STAGE 3
177+
178+
#undef XTENSA_MARCH_LATEST
179+
#define XTENSA_MARCH_LATEST 281050
180+
181+
#undef XTENSA_MARCH_EARLIEST
182+
#define XTENSA_MARCH_EARLIEST 281050
183+
184+
185+
#endif /* !XTENSA_CONFIG_H */

0 commit comments

Comments
 (0)