meta-zephyr-sdk: xilinx_qemu: Enable CPU timers and emaclite for MB-V

Model available in Xilinx v2025.1 version is missing CPU timers which can
be used by Zephyr that's why wire them.
And also enable EMACLITE network IP to have model for it available.

Signed-off-by: Michal Simek <michal.simek@amd.com>

Author: michalsimek

meta-zephyr-sdk/recipes-devtools/qemu_xilinx/files/0003-riscvXX-softmmu-Enable-emaclite-driver-for-MB-V.patch

@@ -0,0 +1,42 @@
+From 42593cded8643f4bd365a51c7d83fec601e49167 Mon Sep 17 00:00:00 2001
+Message-ID: <42593cded8643f4bd365a51c7d83fec601e49167.1747662482.git.michal.simek@amd.com>
+From: Michal Simek <michal.simek@amd.com>
+Date: Fri, 25 Apr 2025 09:24:48 +0200
+Subject: [PATCH] riscvXX-softmmu: Enable emaclite driver for MB-V
+
+Emaclite can be also wired with MB-V that's why enable it by default.
+
+Signed-off-by: Michal Simek <michal.simek@amd.com>
+Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
+---
+ configs/devices/riscv32-softmmu/default.mak | 1 +
+ configs/devices/riscv64-softmmu/default.mak | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/configs/devices/riscv32-softmmu/default.mak b/configs/devices/riscv32-softmmu/default.mak
+index c6c3dcd4431a..7845858ae87c 100644
+--- a/configs/devices/riscv32-softmmu/default.mak
++++ b/configs/devices/riscv32-softmmu/default.mak
+@@ -33,6 +33,7 @@ CONFIG_XILINX_IOMODULE_PIT=y
+ CONFIG_XILINX_IOMODULE_GPI=y
+ CONFIG_XILINX_IOMODULE_GPO=y
+ CONFIG_XILINX_IOMODULE_INTC=y
++CONFIG_XILINX_ETHLITE=y
+ 
+ CONFIG_XLNX_ZYNQMP=y
+ CONFIG_XLNX_VERSAL=y
+diff --git a/configs/devices/riscv64-softmmu/default.mak b/configs/devices/riscv64-softmmu/default.mak
+index 4886ca35dcb7..4f5528eeda9a 100644
+--- a/configs/devices/riscv64-softmmu/default.mak
++++ b/configs/devices/riscv64-softmmu/default.mak
+@@ -20,6 +20,7 @@ CONFIG_XILINX=y
+ CONFIG_SSI=y
+ CONFIG_I2C=y
+ CONFIG_XILINX_AXI=y
++CONFIG_XILINX_ETHLITE=y
+ CONFIG_XILINX_SPI=y
+ CONFIG_XILINX_SPIPS=y
+ CONFIG_PTIMER=y
+-- 
+2.43.0
+

meta-zephyr-sdk/recipes-devtools/qemu_xilinx/files/0004-riscv-Wire-CPU-timers.patch

@@ -0,0 +1,66 @@
+From 2b117b43bb34d5da17d096504c518ab5eaa362f0 Mon Sep 17 00:00:00 2001
+Message-ID: <2b117b43bb34d5da17d096504c518ab5eaa362f0.1747662482.git.michal.simek@amd.com>
+From: Michal Simek <michal.simek@amd.com>
+Date: Fri, 25 Apr 2025 09:54:45 +0200
+Subject: [PATCH] riscv: Wire CPU timers
+
+Our HW is supporting them and FDT model is not wiring them.
+
+Signed-off-by: Michal Simek <michal.simek@amd.com>
+---
+ target/riscv/cpu.c | 25 +++++++++++++------------
+ 1 file changed, 13 insertions(+), 12 deletions(-)
+
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index 2685728f8a28..3bd69a961830 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -553,6 +553,18 @@ static void rv128_base_cpu_init(Object *obj)
+ #endif
+ }
+ #else
++#ifndef CONFIG_USER_ONLY
++static uint64_t mb_v_rdtime(void *opaque)
++{
++    CPURISCVState *env = &RISCV_CPU(opaque)->env;
++    uint32_t time, timeh;
++
++    csr_ops[CSR_MCYCLE].read(env, CSR_MCYCLE, &time);
++    csr_ops[CSR_MCYCLEH].read(env, CSR_MCYCLEH, &timeh);
++    return (uint64_t) timeh << 32 | time;
++}
++#endif
++
+ static void rv32_base_cpu_init(Object *obj)
+ {
+     CPURISCVState *env = &RISCV_CPU(obj)->env;
+@@ -562,6 +574,7 @@ static void rv32_base_cpu_init(Object *obj)
+     env->priv_ver = PRIV_VERSION_LATEST;
+ #ifndef CONFIG_USER_ONLY
+     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
++    riscv_cpu_set_rdtime_fn(env, mb_v_rdtime, obj);
+ #endif
+ }
+ 
+@@ -634,18 +647,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
+     cpu->cfg.pmp = true;
+ }
+ 
+-#ifndef CONFIG_USER_ONLY
+-static uint64_t mb_v_rdtime(void *opaque)
+-{
+-    CPURISCVState *env = &RISCV_CPU(opaque)->env;
+-    uint32_t time, timeh;
+-
+-    csr_ops[CSR_MCYCLE].read(env, CSR_MCYCLE, &time);
+-    csr_ops[CSR_MCYCLEH].read(env, CSR_MCYCLEH, &timeh);
+-    return (uint64_t) timeh << 32 | time;
+-}
+-#endif
+-
+ static void rv32_microblaze_v_cpu_init(Object *obj)
+ {
+ #ifndef CONFIG_USER_ONLY
+-- 
+2.43.0
+

meta-zephyr-sdk/recipes-devtools/qemu_xilinx/qemu-xilinx_git.bb

@@ -14,6 +14,8 @@ SRC_URI += "gitsm://github.com/Xilinx/qemu.git;protocol=https;nobranch=1;name=qe
            file://0004-configure-Add-pkg-config-handling-for-libgcrypt.patch \
            file://0001-Revert-target-arm-Revert-back-to-YIELD-for-WFI.patch \
            file://0002-Enable-WFI-CPU-halting-in-icount-mode.patch \
+           file://0003-riscvXX-softmmu-Enable-emaclite-driver-for-MB-V.patch \
+           file://0004-riscv-Wire-CPU-timers.patch \
            file://0008-tests-meson.build-use-relative-path-to-refer-to-file.patch \
            file://fixedmeson.patch \
            file://no-pip.patch \