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dbalutanashif
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xtensa: add rt500_adsp toolchain
This adds the Xtensa toolchain for Tensilica Fusion F1 DSP found on NXP RT500 MCU family. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
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.github/workflows/ci.yml

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@@ -57,6 +57,7 @@ on:
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- xtensa-intel_tgl_adsp_zephyr-elf
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- xtensa-nxp_imx_adsp_zephyr-elf
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- xtensa-nxp_imx8m_adsp_zephyr-elf
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- xtensa-nxp_rt500_adsp_zephyr-elf
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- xtensa-sample_controller_zephyr-elf
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debug:
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description: 'Debug'
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xtensa-intel_tgl_adsp_zephyr-elf) build_target_xtensa_intel_tgl_adsp_zephyr_elf="y";;
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xtensa-nxp_imx_adsp_zephyr-elf) build_target_xtensa_nxp_imx_adsp_zephyr_elf="y";;
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xtensa-nxp_imx8m_adsp_zephyr-elf) build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y";;
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xtensa-nxp_rt500_adsp_zephyr-elf) build_target_xtensa_nxp_rt500_adsp_zephyr_elf="y";;
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xtensa-sample_controller_zephyr-elf) build_target_xtensa_sample_controller_zephyr_elf="y";;
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esac
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build_target_xtensa_intel_tgl_adsp_zephyr_elf="y"
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build_target_xtensa_nxp_imx_adsp_zephyr_elf="y"
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build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y"
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build_target_xtensa_nxp_rt500_adsp_zephyr_elf="y"
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build_target_xtensa_sample_controller_zephyr_elf="y"
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fi
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[ "${build_target_xtensa_intel_tgl_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_tgl_adsp_zephyr-elf",'
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[ "${build_target_xtensa_nxp_imx_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx_adsp_zephyr-elf",'
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[ "${build_target_xtensa_nxp_imx8m_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8m_adsp_zephyr-elf",'
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[ "${build_target_xtensa_nxp_rt500_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_rt500_adsp_zephyr-elf",'
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[ "${build_target_xtensa_sample_controller_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-sample_controller_zephyr-elf",'
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MATRIX_TARGETS+=']'
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xtensa-nxp_imx8m_adsp_zephyr-elf)
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PLATFORM_ARGS+="-p nxp_adsp_imx8m "
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;;
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xtensa-nxp_rt500_adsp_zephyr-elf)
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PLATFORM_ARGS+="-p nxp_adsp_rt500 "
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;;
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xtensa-sample_controller_zephyr-elf)
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PLATFORM_ARGS+="-p qemu_xtensa "
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;;

README.md

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@@ -15,7 +15,7 @@ The toolchains for the following target architectures are supported:
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- SPARC (32-bit and 64-bit; SPARC V8, SPARC V9)
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- x86 (32-bit and 64-bit)
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- Xtensa (sample_controller, intel_ace15_mtpm, intel_tgl_adsp,
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nxp_imx_adsp, nxp_imx8m_adsp, espressif_esp32, espressif_esp32s2,
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nxp_imx_adsp, nxp_imx8m_adsp, nxp_rt500_adsp, espressif_esp32, espressif_esp32s2,
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espressif_esp32s3)
2020

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The following host tools are available as part of the Zephyr SDK:
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CT_CONFIG_VERSION="3"
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CT_EXPERIMENTAL=y
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CT_OVERLAY_LOCATION="overlays"
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CT_OVERLAY_NAME="nxp_rt500_adsp"
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CT_ARCH_XTENSA=y
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CT_XTENSA_CUSTOM=y
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CT_TARGET_VENDOR="nxp_rt500_adsp_zephyr"
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CT_TARGET_CFLAGS="-ftls-model=local-exec"
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CT_CC_GCC_CONFIG_TLS=n

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