Skip to content

Commit 401b410

Browse files
committed
scripts: llvm: Add initial RISC-V support
This commit adds the initial RISC-V architecture support to the Clang/LLVM build script. Note that only the most basic multi-lib variant (`rvX_zicsr_zifencei`) for each base ISA is built at this time. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
1 parent 45f9287 commit 401b410

File tree

1 file changed

+76
-7
lines changed

1 file changed

+76
-7
lines changed

scripts/llvm/CMakeLists.txt

Lines changed: 76 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -189,7 +189,7 @@ set(LLVM_TOOLCHAIN_DISTRIBUTION_COMPONENTS
189189
installed by the install-llvm-toolchain target"
190190
)
191191
set(LLVM_ENABLE_PROJECTS clang;lld CACHE STRING "")
192-
set(LLVM_TARGETS_TO_BUILD AArch64;ARM CACHE STRING "")
192+
set(LLVM_TARGETS_TO_BUILD AArch64;ARM;RISCV CACHE STRING "")
193193
set(LLVM_DEFAULT_TARGET_TRIPLE aarch64-linux-gnu CACHE STRING "")
194194
set(LLVM_APPEND_VC_REV OFF CACHE BOOL "")
195195
set(LLVM_ENABLE_TERMINFO OFF CACHE BOOL "")
@@ -524,7 +524,11 @@ set(LLVM_DEFAULT_EXTERNAL_LIT "${LLVM_BINARY_DIR}/bin/llvm-lit")
524524
add_custom_target(check-newlib) # FIXME: put things in this
525525

526526
function(get_test_executor_params target_triple qemu_machine qemu_cpu qemu_params)
527-
if(target_triple MATCHES "^aarch64")
527+
if(target_triple MATCHES "^riscv32")
528+
set(qemu_command "qemu-system-riscv32")
529+
elseif(target_triple MATCHES "^riscv64")
530+
set(qemu_command "qemu-system-riscv64")
531+
elseif(target_triple MATCHES "^aarch64")
528532
set(qemu_command "qemu-system-aarch64")
529533
else()
530534
set(qemu_command "qemu-system-arm")
@@ -567,7 +571,13 @@ function(
567571
set(MESON_INSTALL_QUIET "--quiet")
568572
endif()
569573

570-
if(target_triple MATCHES "^aarch64")
574+
if(target_triple MATCHES "^riscv32")
575+
set(cpu_family riscv32)
576+
set(enable_long_double_test true)
577+
elseif(target_triple MATCHES "^riscv64")
578+
set(cpu_family riscv64)
579+
set(enable_long_double_test true)
580+
elseif(target_triple MATCHES "^aarch64")
571581
set(cpu_family aarch64)
572582
set(enable_long_double_test false)
573583
else()
@@ -952,7 +962,7 @@ function(
952962
# Exceptions are architectures pre-armv7, which compiler-rt expects to
953963
# see in the triple because that's where it looks to decide whether to
954964
# use specific assembly sources.
955-
if(NOT target_triple MATCHES "^(aarch64-none-elf|arm-none-eabi|armv[4-6])")
965+
if(NOT target_triple MATCHES "^(aarch64-none-elf|arm-none-eabi|armv[4-6]|riscv32-none-elf|riscv64-none-elf)")
956966
message(FATAL_ERROR "\
957967
Target triple name \"${target_triple}\" not compatible with compiler-rt.
958968
Use -march to specify the architecture.")
@@ -1176,7 +1186,11 @@ function(add_libcxx_libcxxabi_libunwind_tests variant)
11761186
endfunction()
11771187

11781188
function(get_compiler_rt_target_triple target_arch flags)
1179-
if(target_arch MATCHES "^aarch64")
1189+
if(target_arch MATCHES "^rv32")
1190+
set(target_triple "riscv32-none-elf")
1191+
elseif(target_arch MATCHES "^rv64")
1192+
set(target_triple "riscv64-none-elf")
1193+
elseif(target_arch MATCHES "^aarch64")
11801194
set(target_triple "aarch64-none-elf")
11811195
else()
11821196
# Choose the target triple so that compiler-rt will do the
@@ -1247,7 +1261,11 @@ function(add_library_variant target_arch)
12471261
endif()
12481262
endif()
12491263

1250-
if(target_arch MATCHES "^aarch64")
1264+
if(target_arch MATCHES "^rv32")
1265+
set(parent_dir_name riscv32-none-elf)
1266+
elseif(target_arch MATCHES "^rv64")
1267+
set(parent_dir_name riscv64-none-elf)
1268+
elseif(target_arch MATCHES "^aarch64")
12511269
set(parent_dir_name aarch64-none-elf)
12521270
else()
12531271
set(parent_dir_name arm-none-eabi)
@@ -1748,7 +1766,58 @@ add_library_variants_for_cpu(
17481766
RAM_SIZE 0x1000000
17491767
STACK_SIZE 4K
17501768
)
1751-
1769+
# RISC-V multilibs
1770+
## RV32I
1771+
add_library_variants_for_cpu(
1772+
rv32i_zicsr_zifencei
1773+
COMPILE_FLAGS "-march=rv32i_zicsr_zifencei -mabi=ilp32"
1774+
MULTILIB_FLAGS "--target=riscv32-unknown-none-elf"
1775+
PICOLIBC_BUILD_TYPE "release"
1776+
QEMU_MACHINE "none"
1777+
QEMU_CPU "rv32"
1778+
QEMU_PARAMS "-m 1G"
1779+
BOOT_FLASH_ADDRESS 0x00000000
1780+
BOOT_FLASH_SIZE 0x1000
1781+
FLASH_ADDRESS 0x20000000
1782+
FLASH_SIZE 0x1000000
1783+
RAM_ADDRESS 0x21000000
1784+
RAM_SIZE 0x1000000
1785+
STACK_SIZE 4K
1786+
)
1787+
## RV32E
1788+
add_library_variants_for_cpu(
1789+
rv32e_zicsr_zifencei
1790+
COMPILE_FLAGS "-march=rv32e_zicsr_zifencei -mabi=ilp32e"
1791+
MULTILIB_FLAGS "--target=riscv32-unknown-none-elf"
1792+
PICOLIBC_BUILD_TYPE "release"
1793+
QEMU_MACHINE "none"
1794+
QEMU_CPU "rv32"
1795+
QEMU_PARAMS "-m 1G"
1796+
BOOT_FLASH_ADDRESS 0x00000000
1797+
BOOT_FLASH_SIZE 0x1000
1798+
FLASH_ADDRESS 0x20000000
1799+
FLASH_SIZE 0x1000000
1800+
RAM_ADDRESS 0x21000000
1801+
RAM_SIZE 0x1000000
1802+
STACK_SIZE 4K
1803+
)
1804+
## RV64I
1805+
add_library_variants_for_cpu(
1806+
rv64i_zicsr_zifencei
1807+
COMPILE_FLAGS "-march=rv64i_zicsr_zifencei -mabi=lp64 -mcmodel=medany"
1808+
MULTILIB_FLAGS "--target=riscv64-unknown-none-elf"
1809+
PICOLIBC_BUILD_TYPE "release"
1810+
QEMU_MACHINE "none"
1811+
QEMU_CPU "rv64"
1812+
QEMU_PARAMS "-m 1G"
1813+
BOOT_FLASH_ADDRESS 0x00000000
1814+
BOOT_FLASH_SIZE 0x1000
1815+
FLASH_ADDRESS 0x20000000
1816+
FLASH_SIZE 0x1000000
1817+
RAM_ADDRESS 0x21000000
1818+
RAM_SIZE 0x1000000
1819+
STACK_SIZE 4K
1820+
)
17521821

17531822
configure_file(
17541823
${CMAKE_CURRENT_SOURCE_DIR}/cmake/multilib.yaml.in

0 commit comments

Comments
 (0)