From 0e2edeeeb645771e3968dba4dad36f7803e1e5cb Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Fri, 11 Jul 2025 16:57:09 +0800 Subject: [PATCH] mcux-sdk-ng: update netc driver to the latest Updated netc driver to the latest SDK commit. 5309b12e [MCUX-80906] drivers: netc: enable ring0 for EP supporting tag Signed-off-by: Yangbo Lu --- mcux/mcux-sdk-ng/drivers/netc/CMakeLists.txt | 3 +- mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h | 459 +++++++------ .../drivers/netc/fsl_netc_endpoint.c | 112 ++-- .../drivers/netc/fsl_netc_endpoint.h | 109 +++- mcux/mcux-sdk-ng/drivers/netc/fsl_netc_ierb.c | 4 +- mcux/mcux-sdk-ng/drivers/netc/fsl_netc_ierb.h | 8 +- mcux/mcux-sdk-ng/drivers/netc/fsl_netc_mdio.c | 8 +- mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.c | 8 +- mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.h | 5 +- .../drivers/netc/fsl_netc_phy_wrapper.c | 553 +--------------- .../drivers/netc/fsl_netc_phy_wrapper.h | 23 + .../drivers/netc/fsl_netc_switch.c | 370 +++++++---- .../drivers/netc/fsl_netc_switch.h | 329 ++++++++-- mcux/mcux-sdk-ng/drivers/netc/fsl_netc_tag.h | 120 ++++ .../mcux-sdk-ng/drivers/netc/fsl_netc_timer.c | 25 +- .../mcux-sdk-ng/drivers/netc/fsl_netc_timer.h | 10 +- .../drivers/netc/netc_hw/fsl_netc_hw.c | 81 ++- .../drivers/netc/netc_hw/fsl_netc_hw.h | 36 +- .../drivers/netc/netc_hw/fsl_netc_hw_port.c | 90 ++- .../drivers/netc/netc_hw/fsl_netc_hw_port.h | 142 +++- .../drivers/netc/netc_hw/fsl_netc_hw_si.h | 29 +- .../drivers/netc/socs/imx943/fsl_netc_soc.c | 509 ++++++++++++++- .../drivers/netc/socs/imx943/fsl_netc_soc.h | 28 +- .../drivers/netc/socs/imx95/fsl_netc_soc.c | 605 +++++++++++++++--- .../drivers/netc/socs/imx95/fsl_netc_soc.h | 16 +- .../netc/socs/imxrt1180/fsl_netc_soc.c | 26 +- .../netc/socs/imxrt1180/fsl_netc_soc.h | 30 +- 27 files changed, 2512 insertions(+), 1226 deletions(-) create mode 100644 mcux/mcux-sdk-ng/drivers/netc/fsl_netc_tag.h diff --git a/mcux/mcux-sdk-ng/drivers/netc/CMakeLists.txt b/mcux/mcux-sdk-ng/drivers/netc/CMakeLists.txt index c20b241ead..65194c52da 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/CMakeLists.txt +++ b/mcux/mcux-sdk-ng/drivers/netc/CMakeLists.txt @@ -30,7 +30,7 @@ if(CONFIG_MCUX_COMPONENT_driver.netc_imx943) endif() if(CONFIG_MCUX_COMPONENT_driver.netc) - mcux_component_version(2.8.1) + mcux_component_version(2.9.0) mcux_add_source( SOURCES @@ -63,6 +63,7 @@ if(CONFIG_MCUX_COMPONENT_driver.netc_switch) mcux_add_source( SOURCES fsl_netc_switch.h + fsl_netc_tag.h fsl_netc_switch.c ) diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h index 033286af6d..7f9a49a3da 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h @@ -1,5 +1,5 @@ /* - * Copyright 2021-2024 NXP + * Copyright 2021-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -50,10 +50,10 @@ */ /*! @brief Driver Version */ -#define FSL_NETC_DRIVER_VERSION (MAKE_VERSION(2, 8, 1)) +#define FSL_NETC_DRIVER_VERSION (MAKE_VERSION(2, 9, 0)) /*! @brief Macro to divides an address into a low 32 bits and a possible high 32 bits */ -#define NETC_ADDR_LOW_32BIT(x) ((uint32_t)(x)&0xFFFFFFFFU) +#define NETC_ADDR_LOW_32BIT(x) ((uint32_t)(x) & 0xFFFFFFFFU) #define NETC_ADDR_HIGH_32BIT(x) ((4U != sizeof(uintptr_t)) ? (((uintptr_t)(x) >> 32U) & 0xFFFFFFFFU) : 0U) /*! @brief Status code for the NETC module */ @@ -67,9 +67,9 @@ enum MAKE_STATUS(kStatusGroup_NETC, 4), /*!< Lack of resources to configure certain features. */ kStatus_NETC_Unsupported = MAKE_STATUS(kStatusGroup_NETC, 5), /*!< Unsupported operation/feature. */ kStatus_NETC_RxHRZeroFrame = MAKE_STATUS(kStatusGroup_NETC, 6), /*!< Rx frame host reason is zero */ - kStatus_NETC_RxHRNotZeroFrame = MAKE_STATUS(kStatusGroup_NETC, 7), /*!< Rx frame host reason is not zero */ - kStatus_NETC_NotFound = MAKE_STATUS(kStatusGroup_NETC, 8), /*!< No entry found in hardware tables */ - kStatus_NETC_EntryExists = MAKE_STATUS(kStatusGroup_NETC, 9) /*!< An entry already exists in hardware tables */ + kStatus_NETC_RxHRNotZeroFrame = MAKE_STATUS(kStatusGroup_NETC, 7), /*!< Rx frame host reason is not zero */ + kStatus_NETC_NotFound = MAKE_STATUS(kStatusGroup_NETC, 8), /*!< No entry found in hardware tables */ + kStatus_NETC_EntryExists = MAKE_STATUS(kStatusGroup_NETC, 9) /*!< An entry already exists in hardware tables */ }; /*! @brief Defines the common interrupt event for callback use. */ @@ -179,9 +179,11 @@ typedef struct _netc_tx_frame_info_struct { bool isTsAvail; /*!< Tx frame timestamp is available or not. */ uint32_t timestamp; /*!< The timestamp of this Tx frame, valid when isTsAvail is true. */ +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) bool isTxTsIdAvail; /*!< Switch port Tx frame timestamp Identifier is available or not. */ uint16_t txtsid; /*!< The Transmit Timestamp Identifier, valid when isTsIdAvail is true, use for Switch management ENETC direct frame which has specified a timestamp request. */ +#endif void *context; /*!< Private context provided by the user. */ netc_ep_tx_status_t status; /*!< Transmit status. */ } netc_tx_frame_info_t; @@ -205,7 +207,7 @@ typedef struct _netc_msix_entry /*! @brief METC Extension Transmit Buffer Descriptor Extension flags field */ typedef enum _netc_tx_ext_flags { - kNETC_TxExtVlanInsert = 0x1, /*!< Enable VLAN insert. */ + kNETC_TxExtVlanInsert = 0x1, /*!< Enable VLAN insert. */ #if !(defined(FSL_FEATURE_NETC_HAS_ERRATA_051255) && FSL_FEATURE_NETC_HAS_ERRATA_051255) kNETC_TxExtOneStepTs = 0x1 << 1U, /*!< Enable one-step timestamp offload. */ #endif @@ -226,7 +228,7 @@ typedef enum _netc_tx_ext_flags /*! @brief Get SI information from netc_hw_si_idx_t. */ #define getSiInstance(si) ((uint8_t)((uint16_t)(si) >> 8U)) /*!< The ENETC instance of this SI. */ #define getSiNum(si) ((uint8_t)(((uint16_t)(si) >> 4U) & 0xFU)) /*!< The SI number in the ENETC. */ -#define getSiIdx(si) ((uint8_t)((uint16_t)(si)&0xFU)) /*!< The actaul index in the netc_hw_si_idx_t. */ +#define getSiIdx(si) ((uint8_t)((uint16_t)(si) & 0xFU)) /*!< The actaul index in the netc_hw_si_idx_t. */ /*! @brief ENETC index enumerator */ typedef enum _netc_hw_enetc_idx @@ -336,6 +338,7 @@ typedef enum _netc_hw_mii_mode kNETC_GmiiMode = 2U, /*!< GMII mode for data interface. */ kNETC_RmiiMode = 3U, /*!< RMII mode for data interface. */ kNETC_RgmiiMode = 4U, /*!< RGMII mode for data interface. */ + kNETC_SgmiiMode = 5U, /*!< SGMII mode for data interface. */ } netc_hw_mii_mode_t; /*! @brief Defines the speed for the *MII data interface. */ @@ -444,7 +447,7 @@ typedef struct _netc_enetc_native_vlan_config_t bool enUnderZeroVid; /*!< Enable use the port default VLAN VID when the VID in the packet's is zero */ bool enUnderNoVlan; /*!< Enable use the port default VLAN VID when the VLAN tag is not present */ netc_enetc_vlan_tag_t - vlanTag; /*!< Port native outer/inner VLAN tag, valid when enUnderZeroVid or enUnderNoVlan is true */ + vlanTag; /*!< Port native outer/inner VLAN tag, valid when enUnderZeroVid or enUnderNoVlan is true */ } netc_enetc_native_vlan_config_t; /*! @brief ENETC parser configuration */ @@ -478,7 +481,7 @@ typedef enum _netc_port_tgsl_status { kNETC_OperListActive = 0x1U, /*!< Port operational gate control list is active. */ kNETC_AdminListPending = - 0x2U /*!< Administrative gate control list is pending (configured but not installed yet). */ + 0x2U /*!< Administrative gate control list is pending (configured but not installed yet). */ } netc_port_tgsl_status_t; /*! @brief Port Tx/Rx discard counter in the datapath processing pipeline or bridge forwarding processing function*/ @@ -537,6 +540,15 @@ typedef struct _netc_port_tg_config uint32_t holdSkew; /*!< Hold-Skew in ns, not effective on ports connected to a pseudo-MAC */ } netc_port_tg_config_t; +/*! @brief Port time gate config when used with Frame Preemption */ +typedef struct _netc_port_tg_preemption_config +{ + uint16_t holdAdvance; /*!< the amount of time in ns prior to the Set-And-Hold-MAC time slot for asserting a Hold + request. Used with frame Preemption. */ + uint16_t releaseAdvance; /*!< the amount of time in ns prior to the Set-And-Release-MAC time slot for asserting a + Release request. Used with Frame Preemption. */ +} netc_port_tg_preemption_config; + /*! @brief Port MAC preemption mode */ typedef enum _netc_hw_preemption_mode { @@ -545,6 +557,30 @@ typedef enum _netc_hw_preemption_mode kNETC_PreemptOn4B /*!< Frame preemption is enabled, but transmit only preempts frames on 4B boundaries */ } netc_hw_preemption_mode_t; +/*! @brief Port MAC Remote Additional Fragment Size */ +typedef enum _netc_hw_raf_size +{ + kNETC_RafSize64 = 0U, /*!< Additional Fragment Size of 64 octets */ + kNETC_RafSize128, /*!< Additional Fragment Size of 128 octets */ + kNETC_RafSize256, /*!< Additional Fragment Size of 256 octets */ + kNETC_RafSize512, /*!< Additional Fragment Size of 512 octets */ +} netc_hw_raf_size_t; + +/*! @brief Frame Preemption Portconfig */ +typedef struct _netc_port_preemption_config +{ + bool enMergeVerify : 1; /*!< Enable verify the merged preemption frame, need to enable when preemptMode is not zero + */ + uint8_t mergeVerifyTime : 7; /*!< The nominal wait time between verification attempts in milliseconds, range in 1 ~ + 128 */ + netc_hw_preemption_mode_t preemptMode : 2; /*!< When set to not zero, PMAC frames may be preempted by EMAC frames */ + netc_hw_raf_size_t raf_size : 2; /*!< Additional Fragment Size. Indicates the smallest sized fragments that can + be sent on Tx */ + bool PreemptionActive : 1; /*!< Local preemption active. Indicates whether preemption is active for this port. This + bit will be set if preemption is both enabled and has completed the verification + process*/ +} netc_port_preemption_config; + /*! @brief Configuration for the Credit Based Shaped for port TC. * * @note The 802.1Qav bandwidth availability parameters is is calculated as follows: @@ -592,10 +628,10 @@ typedef struct _netc_port_tx_tc_config { bool enPreemption : 1; /*!< Frames from traffic class are transmitted on the preemptable MAC, not supported on internal port (ENETC 1 port and Switch port 4)*/ - bool enTcGate : 1; /*!< Enable the traffic class gate when no gate control list is operational, or when time gate - scheduling is disabled. */ - bool enableTsd : 1; /*!< Enable Time Specific Departure traffic class, only applicable to ENETC */ - bool enableCbs : 1; /*!< Enable Credit based shaper for traffic class */ + bool enTcGate : 1; /*!< Enable the traffic class gate when no gate control list is operational, or when time gate + scheduling is disabled. */ + bool enableTsd : 1; /*!< Enable Time Specific Departure traffic class, only applicable to ENETC */ + bool enableCbs : 1; /*!< Enable Credit based shaper for traffic class */ netc_port_tc_sdu_config_t sduCfg; netc_port_tc_cbs_config_t cbsCfg; /*!< Configure transmit traffic class credit based shaper (PTC0CBSR0/PTC0CBSR1) if enableCbs set to ture */ @@ -660,23 +696,21 @@ typedef struct _netc_port_ethmac { bool enableRevMii : 1; /*!< Enable RevMII mode. */ netc_port_ts_select_t txTsSelect : 1; /*!< Tx timestamp clock source. */ - bool isTsPointPhy : 1; /*!< True: Timestamp is captured based on PHY SFD detect pulse on Rx and Tx for 2-step timestamping. - False: Based on SFD detect at boundary of MAC merge layer and pins/protocol gaskets. */ - netc_hw_mii_mode_t miiMode : 3; /*!< MII mode. */ - netc_hw_mii_speed_t miiSpeed : 3; /*!< MII Speed. */ - netc_hw_mii_duplex_t miiDuplex : 1; /*!< MII duplex. */ + bool isTsPointPhy : 1; /*!< True: Timestamp is captured based on PHY SFD detect pulse on Rx and Tx for 2-step + timestamping. False: Based on SFD detect at boundary of MAC merge layer and pins/protocol + gaskets. */ + netc_hw_mii_mode_t miiMode : 3; /*!< MII mode. */ + netc_hw_mii_speed_t miiSpeed : 3; /*!< MII Speed. */ + netc_hw_mii_duplex_t miiDuplex : 1; /*!< MII duplex. */ bool enTxPad : 1; /*!< Enable ETH MAC Tx Padding, which will pad the frame to a minimum of 60 bytes and append 4 octets of FCS. */ uint8_t rxMinFrameSize : 7; /*!< Receive Minimum Frame Length size in bytes, range in 18 ~ 64, received frames shorter than 18B are discarded silently. Both for express MAC and preemptable MAC. */ uint16_t rxMaxFrameSize; /*!< Receive Maximum Frame Length size in bytes, up to 2000, received frames that exceed this stated maximum are truncated. Both for express MAC and preemptable MAC. */ - bool enMergeVerify : 1; /*!< Enable verify the merged preemption frame, need to enable when preemptMode is not zero - */ - uint8_t mergeVerifyTime : 7; /*!< The nominal wait time between verification attempts in milliseconds, range in 1 ~ - 128 */ - netc_hw_preemption_mode_t preemptMode : 2; /*!< When set to not zero, PMAC frames may be preempted by EMAC frames */ - bool rgmiiClkStop : 1; /*!< True: RGMII transmit clock is stoppable during low power idle. False: It's not stoppable. */ + netc_port_preemption_config PreemptionConfig; /*!< Frame Preemption configuration */ + bool rgmiiClkStop : 1; /*!< True: RGMII transmit clock is stoppable during low power idle. False: It's not + stoppable. */ #if !(defined(FSL_FEATURE_NETC_HAS_ERRATA_051255) && FSL_FEATURE_NETC_HAS_ERRATA_051255) bool enOneStepTS : 1; /*!< Enable IEEE-1588 Single-Step timestamp */ bool enChUpdate : 1; /*!< Enable correction UDP checksum when enable Single-Step timestamp */ @@ -684,15 +718,17 @@ typedef struct _netc_port_ethmac (index to MS byte) */ #endif bool enableHalfDuplexFlowCtrl : 1; /*!< Enable/Disable half-duplex flow control. */ - uint16_t maxBackPressOn; /*!< Maximum amount of time backpressure can stay asserted before stopping to prevent excess - defer on link partner, in byte times. */ + uint16_t maxBackPressOn; /*!< Maximum amount of time backpressure can stay asserted before stopping to prevent + excess defer on link partner, in byte times. */ uint16_t minBackPressOff; /*!< Minimum amount of time backpressure will stay off after reaching the ON max, before - backpressure can reassert after checking if icm_pause_notification is still or again - asserted, in byte times. */ - uint32_t txWakeupTimeCycleEEE; /*!< Energy Efficient Ethernet feature. Defines the number of NETC cycles (which represents time) required by the PHY to wait before - transmitting a new frame after the application has indicated it wants to end the low power state. */ - uint32_t txSleepTimeCycleEEE; /*!< Energy Efficient Ethernet feature. Defines the number of NETC cycles (which represents time) where Tx is idle before mac transmits - low power EEE. A value of 0 does not activate low power EEE transmission. */ + backpressure can reassert after checking if icm_pause_notification is still or + again asserted, in byte times. */ + uint32_t txWakeupTimeCycleEEE; /*!< Energy Efficient Ethernet feature. Defines the number of NETC cycles (which + represents time) required by the PHY to wait before transmitting a new frame after the + application has indicated it wants to end the low power state. */ + uint32_t txSleepTimeCycleEEE; /*!< Energy Efficient Ethernet feature. Defines the number of NETC cycles (which + represents time) where Tx is idle before mac transmits low power EEE. A value of 0 + does not activate low power EEE transmission. */ } netc_port_ethmac_t; /*! @brief Defines the Port's Stream Gate Open Gate Check mode. */ @@ -714,8 +750,8 @@ typedef struct _netc_port_common uint8_t txMacsecBco; /*!< Port transmit MACSec byte count overhead which due to MACSec encapsulation */ uint8_t txPpduBco; /*!< Port transmit PPDU Byte count overhead which includes IPG, SFD and Preamble */ #if (defined(FSL_FEATURE_NETC_HAS_PORT_FCSEA) && FSL_FEATURE_NETC_HAS_PORT_FCSEA) - bool stompFcs : 1; /*!< Enable stomp the FCS error frame, not effective on ports connected to a pseudo-MAC, only - applies to device with ASIL-B safety requirements */ + bool stompFcs : 1; /*!< Enable stomp the FCS error frame, not effective on ports connected to a pseudo-MAC, only + applies to device with ASIL-B safety requirements */ #endif netc_port_sg_ogc_mode_t ogcMode : 1; /*!< Stream Gate Open Gate Check mode, 0b is check whether SFD is within the open gate interval, 1b is check whether the entire frame is within the open gate interval */ @@ -881,8 +917,8 @@ typedef enum _netc_tb_cmd kNETC_AddOrUpdateEntry = 0xAU, /*!< If the entry exists, is update operation, if not exist, is the Add operation*/ kNETC_AddAndQueryEntry = 0xCU, /*!< Add operation followed by a query operation */ kNETC_AddQueryAndUpdateEntry = - 0xEU /*!< Add operation followed by a query operation, Then, if the entry existed - prior to the Add operation of this command, the Update operation will be performed. */ + 0xEU /*!< Add operation followed by a query operation, Then, if the entry existed + prior to the Add operation of this command, the Update operation will be performed. */ } netc_tb_cmd_t; /*! @brief Table Access Method */ @@ -1047,14 +1083,14 @@ typedef union _netc_cmd_bd }; struct { - netc_tb_cmd_t cmd : 4; /*!< Access table entry command, see @ref netc_tb_cmd_t . */ + netc_tb_cmd_t cmd : 4; /*!< Access table entry command, see @ref netc_tb_cmd_t . */ uint32_t : 8; netc_tb_access_mode_t accessType : 2; /*!< Access table entry method, see @ref netc_tb_access_mode_t. */ uint32_t : 2; /*!< RSS Hash high field value. */ netc_tb_index_t tableId : 8; - uint32_t version : 6; /*!< Protocol Version. */ - uint32_t enCompInt : 1; /*!< Command Completion Interrupt. */ - uint32_t resReady : 1; /*!< Response Ready. */ + uint32_t version : 6; /*!< Protocol Version. */ + uint32_t enCompInt : 1; /*!< Command Completion Interrupt. */ + uint32_t resReady : 1; /*!< Response Ready. */ }; uint32_t reserved[3]; struct @@ -1072,26 +1108,26 @@ typedef union _netc_cmd_bd uint32_t numMatched : 16; /*!< Number of Entries Matched. */ uint32_t error : 12; /*!< Error status. */ uint32_t : 3; - uint32_t resReady : 1; /*!< Response Ready. */ + uint32_t resReady : 1; /*!< Response Ready. */ }; uint32_t reserved2[4]; } resp; struct { - uint64_t addr; /*!< Data. */ + uint64_t addr; /*!< Data. */ uint32_t : 31; - uint32_t en : 1; /*!< Enable entry. */ + uint32_t en : 1; /*!< Enable entry. */ uint32_t reserved[2]; uint32_t siBitMap : 16; /*!< Station interfaces 15-0 for which this filter applies. */ uint32_t : 16; - uint32_t index : 16; /*!< The index refers to an entry location within a table. */ - uint32_t length : 16; /*!< NA */ - uint32_t cmd : 8; /*!< Command. */ - uint32_t class : 8; /*!< Class of command. */ + uint32_t index : 16; /*!< The index refers to an entry location within a table. */ + uint32_t length : 16; /*!< NA */ + uint32_t cmd : 8; /*!< Command. */ + uint32_t class : 8; /*!< Class of command. */ uint32_t : 8; - uint32_t status : 6; /*!< Status. */ - uint32_t ci : 1; /*!< Completion interrupt. */ - uint32_t sf : 1; /*!< Short format. */ + uint32_t status : 6; /*!< Status. */ + uint32_t ci : 1; /*!< Completion interrupt. */ + uint32_t sf : 1; /*!< Short format. */ } generic; } netc_cmd_bd_t; @@ -1118,7 +1154,7 @@ typedef struct _netc_tb_common_header { uint32_t updateActions : 16; /*!< Update Actions */ uint32_t : 8; - uint32_t queryActions : 4; /*!< Query Actions */ + uint32_t queryActions : 4; /*!< Query Actions */ uint32_t : 4; } netc_tb_common_header_t; @@ -1168,9 +1204,11 @@ typedef enum _netc_fm_vlan_ar_act * @note sqta should be netc_fm_sqt_act_t type, vuda should be netc_fm_vlan_ud_act_t type and vara should be * netc_fm_vlan_ar_act_t type. */ -#define NETC_FD_EID_ENCODE_OPTION_0(entryId) ((uint32_t)(entryId)&0xFFFU) -#define NETC_FD_EID_ENCODE_OPTION_1(sqta, vuda) ((((uint32_t)(sqta)&0x7U) << 2U) | ((uint32_t)(vuda)&0x3U) | 0x2000U) -#define NETC_FD_EID_ENCODE_OPTION_2(vara, vid) ((((uint32_t)(vara)&0x3U) << 12U) | ((uint32_t)(vid)&0xFFFU) | 0x4000U) +#define NETC_FD_EID_ENCODE_OPTION_0(entryId) ((uint32_t)(entryId) & 0xFFFU) +#define NETC_FD_EID_ENCODE_OPTION_1(sqta, vuda) \ + ((((uint32_t)(sqta) & 0x7U) << 2U) | ((uint32_t)(vuda) & 0x3U) | 0x2000U) +#define NETC_FD_EID_ENCODE_OPTION_2(vara, vid) \ + ((((uint32_t)(vara) & 0x3U) << 12U) | ((uint32_t)(vid) & 0xFFFU) | 0x4000U) /*! * @brief Define FDB/L2MCF/IS table entry access the primary Egress Treatment table entry group mode @@ -1215,8 +1253,8 @@ typedef enum _netc_tb_ipf_attr_mask kNETC_IPFIpHeaderMask = 0x80U, /*!< IP Header Mask */ kNETC_IPFIpVersionMask = 0x100U, /*!< IP Version Mask */ kNETC_IPFIpExtMask = 0x200U, /*!< IPv4 option / IPv6 extension Mask */ - kNETC_IPFL4HeaderMask = 0x400U, /*!< L4 Code Mask */ - kNETC_IPFWakeOnLanMask = 0x800U /*!< Wake-on-LAN Magic Packet Mask */ + kNETC_IPFL4HeaderMask = 0xC00U, /*!< L4 Code Mask */ + kNETC_IPFWakeOnLanMask = 0x1000U /*!< Wake-on-LAN Magic Packet Mask */ } netc_tb_ipf_attr_mask_t; /*! @brief Ingress Port Filter frame attribute Sequence Tag Code */ @@ -1257,35 +1295,35 @@ typedef struct _netc_tb_ipf_keye netc_tb_ipf_l4_header_t l4Header : 2; /*!< L4 Header code */ uint16_t wakeOnLan : 1; /*!< Wake-on-LAN Magic Packet Present */ uint16_t : 3; - } frameAttr; /*!< Frame Attribute flags */ - uint16_t frameAttrMask; /*!< Frame attribute mask, set with OR of @ref netc_tb_ipf_attr_mask_t */ - uint16_t dscp : 6; /*!< Differentiated Services Code Point */ - uint16_t dscpMask : 6; /*!< Differentiated Services Code Point Mask */ + } frameAttr; /*!< Frame Attribute flags */ + uint16_t frameAttrMask; /*!< Frame attribute mask, set with OR of @ref netc_tb_ipf_attr_mask_t */ + uint16_t dscp : 6; /*!< Differentiated Services Code Point */ + uint16_t dscpMask : 6; /*!< Differentiated Services Code Point Mask */ uint16_t res1 : 4; - uint16_t srcPort : 5; /*!< Source Port ID */ - uint16_t srcPortMask : 5; /*!< Source Port ID Mask */ + uint16_t srcPort : 5; /*!< Source Port ID */ + uint16_t srcPortMask : 5; /*!< Source Port ID Mask */ uint16_t res2 : 6; - uint16_t outerVlanTCI; /*!< Outer VLAN Tag Control Information */ - uint16_t outerVlanTCIMask; /*!< Outer VLAN Tag Control Information Mask */ - uint8_t dmac[6]; /*!< Destination MAC Address */ - uint8_t dmacMask[6]; /*!< Destination MAC Address Mask */ - uint8_t smac[6]; /*!< Source MAC Address */ - uint8_t smacMask[6]; /*!< Source MAC Address Mask */ - uint16_t innerVlanTCI; /*!< Inner VLAN Tag Control Information */ - uint16_t innerVlanTCIMask; /*!< Inner VLAN Tag Control Information Mask */ - uint16_t etherType; /*!< 2-byte EtherType */ - uint16_t etherTypeMask; /*!< EtherType Mask */ - uint8_t IPProtocol; /*!< IP Protocol */ - uint8_t IPProtocolMask; /*!< IP Protocol Mask */ + uint16_t outerVlanTCI; /*!< Outer VLAN Tag Control Information */ + uint16_t outerVlanTCIMask; /*!< Outer VLAN Tag Control Information Mask */ + uint8_t dmac[6]; /*!< Destination MAC Address */ + uint8_t dmacMask[6]; /*!< Destination MAC Address Mask */ + uint8_t smac[6]; /*!< Source MAC Address */ + uint8_t smacMask[6]; /*!< Source MAC Address Mask */ + uint16_t innerVlanTCI; /*!< Inner VLAN Tag Control Information */ + uint16_t innerVlanTCIMask; /*!< Inner VLAN Tag Control Information Mask */ + uint16_t etherType; /*!< 2-byte EtherType */ + uint16_t etherTypeMask; /*!< EtherType Mask */ + uint8_t IPProtocol; /*!< IP Protocol */ + uint8_t IPProtocolMask; /*!< IP Protocol Mask */ uint8_t res3[14]; uint8_t srcIPAddr[16]; /*!< IP Source Address, Bits 127-0: IPv6 source address, Bits 127-96: IPv4 source address */ uint8_t res4[8]; - uint8_t srcIPAddrMask[16]; /*!< IP Source Address Mask */ - uint16_t l4SrcPort; /*!< L4 Source Port */ - uint16_t l4SrcPortMask; /*!< L4 Source Port Mask */ + uint8_t srcIPAddrMask[16]; /*!< IP Source Address Mask */ + uint16_t l4SrcPort; /*!< L4 Source Port */ + uint16_t l4SrcPortMask; /*!< L4 Source Port Mask */ uint8_t res5[4]; - uint8_t destIPAddr[16]; /*!< IP Destination Address, Bits 127-0: IPv6 source address, Bits 127-96: IPv4 source - address */ + uint8_t destIPAddr[16]; /*!< IP Destination Address, Bits 127-0: IPv6 source address, Bits 127-96: IPv4 source + address */ uint8_t res6[8]; uint8_t destIPAddrMask[16]; /*!< IP Destination Address Mask*/ uint16_t l4DestPort; /*!< L4 Destination Port */ @@ -1330,16 +1368,16 @@ typedef struct _netc_tb_ipf_cfge uint32_t odr : 1; /*!< Overwrite DR */ netc_tb_ipf_forward_action_t fltfa : 2; /*!< Filter Forwarding action. */ uint32_t : 1; - uint32_t imire : 1; /*!< Ingress Mirroring Enable */ - uint32_t wolte : 1; /*!< Wake-onLAN trigger enable */ - netc_tb_ipf_filter_action_t flta : 2; /*!< FIlter Action. */ - uint32_t rpr : 2; /*!< Relative Precedent Resolution */ - uint32_t ctd : 1; /*!< Cut through disable. */ - netc_host_reason_t hr : 4; /*!< Host Reason metadata when frame is redirected/copied to - the switch management port */ - uint32_t timecape : 1; /*!< Timestam capture enable */ + uint32_t imire : 1; /*!< Ingress Mirroring Enable */ + uint32_t wolte : 1; /*!< Wake-onLAN trigger enable */ + netc_tb_ipf_filter_action_t flta : 2; /*!< FIlter Action. */ + uint32_t rpr : 2; /*!< Relative Precedent Resolution */ + uint32_t ctd : 1; /*!< Cut through disable. */ + netc_host_reason_t hr : 4; /*!< Host Reason metadata when frame is redirected/copied to + the switch management port */ + uint32_t timecape : 1; /*!< Timestam capture enable */ uint32_t : 9; - uint32_t fltaTgt; /*!< Target for selected switch forwarding action or filter action*/ + uint32_t fltaTgt; /*!< Target for selected switch forwarding action or filter action*/ } netc_tb_ipf_cfge_t; /*! @brief Ingress port filter statistic element */ @@ -1398,7 +1436,7 @@ typedef struct _netc_tb_ipf_config /*! @brief 2 Bytes VLAN field which may added to the frame Key */ #define NETC_ISI_VLAN_FRAME_KEY(valid, pcp, vid) \ - (((uint16_t)((valid)&0x1) << 15U) | ((uint16_t)((pcp)&0x3) << 12U) | ((uint16_t)(vid)&0xFFFU)) + (((uint16_t)((valid) & 0x1) << 15U) | ((uint16_t)((pcp) & 0x3) << 12U) | ((uint16_t)(vid) & 0xFFFU)) /*! @brief Stream identification table key type */ typedef enum _netc_tb_isi_key_type @@ -1416,7 +1454,7 @@ typedef struct _netc_tb_isi_keye uint8_t srcPortID : 5; /*!< Source Port ID, used when kc portp filed is 1. Only for SWITCH */ uint8_t spm : 1; /*!< Source Port Masquerading, used when kc spm filed is 1. Only for SWITCH */ uint8_t res0[3]; - uint8_t framekey[16]; /*!< Frame portion of the key. */ + uint8_t framekey[16]; /*!< Frame portion of the key. */ } netc_tb_isi_keye_t; /*! @brief Stream identification table config element */ @@ -1510,14 +1548,14 @@ typedef netc_tb_eteid_access_mode_t netc_tb_is_oeteid_mode_t; /*! @brief Ingress Stream table config element */ typedef struct _netc_tb_is_cfge { - uint32_t sfe : 1; /*!< Stream Filtering Enable */ + uint32_t sfe : 1; /*!< Stream Filtering Enable */ uint32_t : 3; - uint32_t ipv : 4; /*!< Internal Priority Value, active when opiv is set to 1 */ - uint32_t oipv : 1; /*!< Override internal priority value */ - uint32_t dr : 2; /*!< Drop Resilience, active when odr is set to 1 */ - uint32_t odr : 1; /*!< Overwrite DR */ - uint32_t imire : 1; /*!< Ingress Mirroring Enable, not applicable to ENETC */ - uint32_t timecape : 1; /*!< Timestamp Capture Enable, not applicable to ENETC */ + uint32_t ipv : 4; /*!< Internal Priority Value, active when opiv is set to 1 */ + uint32_t oipv : 1; /*!< Override internal priority value */ + uint32_t dr : 2; /*!< Drop Resilience, active when odr is set to 1 */ + uint32_t odr : 1; /*!< Overwrite DR */ + uint32_t imire : 1; /*!< Ingress Mirroring Enable, not applicable to ENETC */ + uint32_t timecape : 1; /*!< Timestamp Capture Enable, not applicable to ENETC */ uint32_t : 1; uint32_t sppd : 1; /*!< Source Port Pruning Disable, not applicable to ENETC */ netc_tb_is_isq_action_t isqa : 2; /*!< Ingress Sequence Action, not applicable to ENETC */ @@ -1529,7 +1567,7 @@ typedef struct _netc_tb_is_cfge netc_tb_is_forward_action_t fa : 3; /*!< Forwad Option */ netc_tc_sdu_type_t sduType : 2; /*!< Service Data Unit Type to user for MSDU */ uint32_t : 3; - uint32_t msdu : 16; /*!< Maximum Service Data Unit */ + uint32_t msdu : 16; /*!< Maximum Service Data Unit */ uint32_t ifmeLenChange : 7; /*!< Ingress Frame Modification Entry Frame Length Change, specified in unit of bytes using a 2's complement notation */ uint32_t eport : 5; /*!< Egress Port which need do egress packet processing, active when oeteid is set to 1, not @@ -1548,7 +1586,7 @@ typedef struct _netc_tb_is_cfge uint32_t ePortBitmap; /*!< Egress Port bitmap, identifies the ports to which the frame is to be forwarding or ET applicability port bitmap when oETEID = 10b. Not applicable to ENETC */ uint32_t : 8; - uint32_t siMap : 16; /*!< Station Interface Map, only valid for ENETC function when fa field is set to 10b */ + uint32_t siMap : 16; /*!< Station Interface Map, only valid for ENETC function when fa field is set to 10b */ uint32_t : 16; } netc_tb_is_cfge_t; @@ -1615,10 +1653,10 @@ typedef struct _netc_tb_isf_cfge uint32_t orp : 1; /*!< Override Rate Policer (instance) ID */ netc_tc_sdu_type_t sduType : 2; /*!< Service Data Unit Type to user for MSDU */ uint32_t : 1; - uint32_t msdu : 16; /*!< Maximum Service Data Unit */ - uint32_t rpEID; /*!< Rate Policer Entry ID, Valid when orp =1. 0xFFFF_FFFF is NULL */ - uint32_t sgiEID; /*!< Stream Gate Instance Entry ID, Valid when osgi =1. 0xFFFF_FFFF is NULL */ - uint32_t iscEID; /*!< Ingress Stream counter Index. 0xFFFF_FFFF is NULL. */ + uint32_t msdu : 16; /*!< Maximum Service Data Unit */ + uint32_t rpEID; /*!< Rate Policer Entry ID, Valid when orp =1. 0xFFFF_FFFF is NULL */ + uint32_t sgiEID; /*!< Stream Gate Instance Entry ID, Valid when osgi =1. 0xFFFF_FFFF is NULL */ + uint32_t iscEID; /*!< Ingress Stream counter Index. 0xFFFF_FFFF is NULL. */ } netc_tb_isf_cfge_t; /*! @brief Ingress Stream Filter table request data buffer */ @@ -1798,13 +1836,13 @@ typedef struct _netc_tb_rp_config /*! @brief Ingress Stream Count table statistic element */ typedef struct _netc_tb_isc_stse { - uint32_t rxCount; /*!< Receive Count */ + uint32_t rxCount; /*!< Receive Count */ uint32_t res0; - uint32_t msduDropCount; /*!< MSDU Drop Count */ + uint32_t msduDropCount; /*!< MSDU Drop Count */ uint32_t res1; uint32_t policerDropCount; /*!< Policer Drop Count */ uint32_t res2; - uint32_t sgDropCount; /*!< Stream Gating Drop Count */ + uint32_t sgDropCount; /*!< Stream Gating Drop Count */ uint32_t res3; } netc_tb_isc_stse_t; @@ -1926,7 +1964,7 @@ typedef struct _netc_tb_sgi_rsp_data netc_tb_sgi_sgise_t sgise; struct { - uint8_t res0[24]; + uint8_t res0[25]; netc_tb_sgi_cfge_t cfge; netc_tb_sgi_icfge_t icfge; uint8_t res1; @@ -1980,8 +2018,8 @@ typedef struct _netc_sgcl_gate_entry /*! @brief Stream Gate Control List table config element */ typedef struct _netc_tb_sgcl_cfge { - uint32_t cycleTime; /*!< Cycle Time */ - uint8_t listLength; /*!< List Length */ + uint32_t cycleTime; /*!< Cycle Time */ + uint8_t listLength; /*!< List Length */ uint8_t res0; uint16_t extOipv : 1; /*!< Extension (means the stream gate control list ends and before cycleTime restarts) Override Internal Priority Value */ @@ -2190,12 +2228,12 @@ typedef struct _netc_tb_fm_cfge netc_tb_fm_outer_dei_act_t outerDeiAct : 2; /*!< Outer DEI action */ netc_tb_fm_payload_act_t pldAct : 3; /*!< Payload Actions, Not applicable for ingress frame modifications */ uint32_t : 5; - uint8_t pldOffset; /*!< Payload Offset, valid if outerPldAct = 010b */ + uint8_t pldOffset; /*!< Payload Offset, valid if outerPldAct = 010b */ uint8_t res1[3]; uint16_t fmdBytes; /*!< Frame Modification Bytes, valid if outerPldAct = 001b,010b or l2Act = 1b */ uint16_t res2; - uint32_t fmdEID; /*!< Frame Modification Data Entry ID, valid if outerPldAct = 001b,010b or l2Act = 1b. 0xFFFF is - null pointer */ + uint32_t fmdEID; /*!< Frame Modification Data Entry ID, valid if outerPldAct = 001b,010b or l2Act = 1b. 0xFFFF is + null pointer */ } netc_tb_fm_cfge_t; /*! @brief Frame Modification table request data buffer */ @@ -2268,7 +2306,7 @@ typedef struct _netc_tb_fmd_data /*! @brief Frame Modification data table entry update config */ typedef struct _netc_tb_fmd_update_config { - uint32_t res; /*!< Hold for request->commonHeader */ + uint32_t res; /*!< Hold for request->commonHeader */ uint32_t entryID; uint8_t cfge[]; /*!< Configuration Element Data size is variable */ } netc_tb_fmd_update_config_t; @@ -2301,18 +2339,18 @@ typedef struct _netc_tb_vf_cfge uint32_t portMembership : 24; /*!< Port Membership Bitmap */ uint32_t stgID : 4; /*!< Spanning Tree Group Member ID */ uint32_t : 4; - uint32_t fid : 12; /*!< Filtering ID */ + uint32_t fid : 12; /*!< Filtering ID */ uint32_t : 4; - uint32_t mlo : 3; /*!< MAC Learning Options */ - uint32_t mfo : 2; /*!< MAC Forwarding Options */ + uint32_t mlo : 3; /*!< MAC Learning Options */ + uint32_t mfo : 2; /*!< MAC Forwarding Options */ uint32_t : 1; - uint32_t ipmfe : 1; /*!< IP Multicast Filtering Enable */ - uint32_t ipmfle : 1; /*!< IP Multicast Flooding Enable */ + uint32_t ipmfe : 1; /*!< IP Multicast Filtering Enable */ + uint32_t ipmfle : 1; /*!< IP Multicast Flooding Enable */ uint32_t : 8; - uint32_t etaPortBitmap : 24; /*!< Egress Treatment Applicability Port Bitmap for the secondary - Egress Treatment group */ + uint32_t etaPortBitmap : 24; /*!< Egress Treatment Applicability Port Bitmap for the secondary + Egress Treatment group */ uint32_t : 8; - uint32_t baseETEID; /*!< Base Egress Treatment Entry ID for the secondary Egress Treatment group */ + uint32_t baseETEID; /*!< Base Egress Treatment Entry ID for the secondary Egress Treatment group */ } netc_tb_vf_cfge_t; /*! @brief Vlan Filter table search criteria format */ @@ -2392,7 +2430,7 @@ typedef struct _netc_tb_fdb_keye uint8_t macAddr[6]; /*!< Destination MAC address of the frame for MAC forwarding lookups and the source MAC address of the frame for MAC learning lookups */ uint8_t res0[2]; - uint32_t fid : 12; /*!< Filtering ID, is obtained from an ingress lookup into the VLAN Filter table */ + uint32_t fid : 12; /*!< Filtering ID, is obtained from an ingress lookup into the VLAN Filter table */ uint32_t : 20; } netc_tb_fdb_keye_t; @@ -2406,9 +2444,9 @@ typedef struct _netc_tb_fdb_cfge uint32_t ePort : 5; /*!< Egress Ports, active when oETEid = 01b or ctd = 01b */ uint32_t iMirE : 1; /*!< Ingress Mirroring Enable */ uint32_t : 1; - netc_tb_fdb_ctd_mode_t ctd : 2; /*!< Cut-Through Disable */ - uint32_t dynamic : 1; /*!< Static or Dynamic Entry, 0b = Static entry, 1b = Dynamic entry */ - uint32_t timeCapE : 1; /*!< Timestamp Capture Enable when set */ + netc_tb_fdb_ctd_mode_t ctd : 2; /*!< Cut-Through Disable */ + uint32_t dynamic : 1; /*!< Static or Dynamic Entry, 0b = Static entry, 1b = Dynamic entry */ + uint32_t timeCapE : 1; /*!< Timestamp Capture Enable when set */ uint32_t : 19; uint32_t etEID; /*!< Base egress treatment table entry id for primary Egress Treatment group, is valid if the oETEID field is set to value other than kNETC_FDBNoEPP. 0xFFFFFFFF is NULL. */ @@ -2455,7 +2493,7 @@ typedef struct _netc_tb_fdb_search_criteria netc_tb_fdb_cfge_t cfge; /*!< Configuration Element data which used to match against the table entries */ struct { - netc_tb_fdb_acte_t acte; /*!< Activity Element data which used to match against the table entries */ + netc_tb_fdb_acte_t acte; /*!< Activity Element data which used to match against the table entries */ netc_tb_fdb_sc_keye_mc_t keyeMc : 2; /*!< Key Element data match criteria */ uint8_t : 6; netc_tb_fdb_sc_cfge_mc_t cfgeMc : 3; /*!< Configuration Element data match criteria */ @@ -2476,7 +2514,7 @@ typedef struct _netc_tb_fdb_req_data netc_tb_fdb_keye_t keye; /*!< Active when access method is kNETC_ExactKeyMatch */ netc_tb_fdb_search_criteria_t sCriteria; /*!< Active when access method is kNETC_Search */ }; - netc_tb_fdb_cfge_t cfge; /*!< Present only for commands which perform an update or add */ + netc_tb_fdb_cfge_t cfge; /*!< Present only for commands which perform an update or add */ } netc_tb_fdb_req_data_t; /*! @brief FDB table request response data buffer */ @@ -2527,10 +2565,10 @@ typedef struct _netc_tb_l2mcf_keye { netc_tb_l2mcf_key_type_t keyType : 4; /*!< Key Type */ uint32_t : 12; - uint32_t fid : 12; /*!< Filtering ID */ + uint32_t fid : 12; /*!< Filtering ID */ uint32_t : 4; - uint32_t ipv4DestAddr; /*!< IPv4 Destination Address */ - uint32_t ipv4SrcAddr; /*!< IPv4 Source Address */ + uint32_t ipv4DestAddr; /*!< IPv4 Destination Address */ + uint32_t ipv4SrcAddr; /*!< IPv4 Source Address */ } netc_tb_l2mcf_keye_t; /*! @brief L2 IPV4 Multicast Filter table search criteria Key Element Match Criteria */ @@ -2687,7 +2725,7 @@ typedef struct _netc_tb_iseqg_config typedef enum _netc_tb_iseqg_update_action { kNETC_ISEQGCfgEUpdate = 0x1U, /*!< Configuration Element Update */ - kNETC_ISEQGSgsEUpdate = 0x2U, /*!< Sequence Generation Element Update */ + kNETC_ISEQGSgsEUpdate = 0x2U, /*!< Sequence Generation Element Update */ } netc_tb_iseqg_update_action_t; #if !(defined(__GNUC__) || defined(__ICCARM__)) @@ -2715,11 +2753,11 @@ typedef struct _netc_tb_eseqr_cfge uint32_t sqrType : 1; /*!< Sequence Recovery Function type, 0b = Sequence recovery function, 1b = Individual recovery function */ uint32_t : 2; - uint32_t sqrHl : 7; /*!< Sequence Recovery History Length, valid if sqrAlg = 0b */ + uint32_t sqrHl : 7; /*!< Sequence Recovery History Length, valid if sqrAlg = 0b */ uint32_t : 1; uint32_t sqrFwl : 12; /*!< Sequence Recovery Future Window Length, valid if sqrAlg = 0b */ uint32_t : 4; - uint32_t sqrTp : 12; /*!< Sequence Timeout Period, the unit is 1.048576 milliseconds */ + uint32_t sqrTp : 12; /*!< Sequence Timeout Period, the unit is 1.048576 milliseconds */ uint32_t : 20; } netc_tb_eseqr_cfge_t; @@ -2738,10 +2776,10 @@ typedef struct _netc_tb_eseqr_stse /*! @brief Egress Sequence Recovery table sequence recovery state element */ typedef struct _netc_tb_eseqr_srse { - uint32_t sqrNum : 16; /*!< Sequence Recovery Number */ - uint32_t takeAny : 1; /*!< Take Any */ - uint32_t lce : 1; /*!< Lost Count Enable */ - uint32_t sqrTs : 12; /*!< Sequence Recovery Timestamp */ + uint32_t sqrNum : 16; /*!< Sequence Recovery Number */ + uint32_t takeAny : 1; /*!< Take Any */ + uint32_t lce : 1; /*!< Lost Count Enable */ + uint32_t sqrTs : 12; /*!< Sequence Recovery Timestamp */ uint32_t : 2; uint32_t sqrHistory[4]; /*!< Recovery History bit vector, each bit corresponding to sequence numbers, bit 1 means a packet with that sequence number has been previously received */ @@ -2820,8 +2858,8 @@ typedef struct _netc_tgs_gate_entry { struct { - uint32_t tcGateState : 8; /*!< Traffic Class Gate States for Gate Entry, 8 bits for 8 Traffic - Class , 0b means Gate closed, 1b means Gate open */ + uint32_t tcGateState : 8; /*!< Traffic Class Gate States for Gate Entry, 8 bits for 8 Traffic + Class , 0b means Gate closed, 1b means Gate open */ uint32_t : 8; netc_tb_tgs_gate_type_t operType : 4; /*!< Gate operation type ( IEEE 802.1Q-2018) field for gate control list entry i */ @@ -2939,16 +2977,16 @@ typedef struct _netc_tb_et_cfge { netc_tb_et_efm_mode_t efmMode : 2; /*!< Egress Frame Modification mode */ uint8_t : 2; - netc_tb_et_esq_act_t esqa : 2; /*!< Egress Sequence Actions */ - netc_tb_et_ec_act_t eca : 2; /*!< Egress Counter Action */ - uint8_t : 1; /*!< Reserve for data align */ - uint8_t efmLenChange : 7; /*!< Egress Frame Modification Length Change, specified in units of bytes using a 2's - complement notation */ - uint16_t efmDataLen : 11; /*!< Egress Frame Modification Data Length */ + netc_tb_et_esq_act_t esqa : 2; /*!< Egress Sequence Actions */ + netc_tb_et_ec_act_t eca : 2; /*!< Egress Counter Action */ + uint8_t : 1; /*!< Reserve for data align */ + uint8_t efmLenChange : 7; /*!< Egress Frame Modification Length Change, specified in units of bytes using a 2's + complement notation */ + uint16_t efmDataLen : 11; /*!< Egress Frame Modification Data Length */ uint16_t : 5; - uint32_t efmEID; /*!< Egress Frame Modification Entry Id */ - uint32_t ecEID; /*!< Egress Count Table Entry ID */ - uint32_t esqaTgtEID; /*!< Egress Sequence Actions Target Entry ID, active when esqa = 10b */ + uint32_t efmEID; /*!< Egress Frame Modification Entry Id */ + uint32_t ecEID; /*!< Egress Count Table Entry ID */ + uint32_t esqaTgtEID; /*!< Egress Sequence Actions Target Entry ID, active when esqa = 10b */ } netc_tb_et_cfge_t; /*! @brief Egress Treatment table request data buffer */ @@ -2992,7 +3030,7 @@ typedef struct _netc_tb_et_config #endif /*! @brief ETM Class Queue table entry ID macro, cqID is represents the Class Queue ID ,rang in 0 ~ 7, portID is Switch * ID, rang in 0 ~ 4 */ -#define NETC_TB_ETM_CQ_ENTRY_ID(portID, cqID) (((uint32_t)(portID) << 4U) | ((cqID)&0x7U)) +#define NETC_TB_ETM_CQ_ENTRY_ID(portID, cqID) (((uint32_t)(portID) << 4U) | ((cqID) & 0x7U)) /*! @brief ETM Class Queue table Update Actions */ typedef enum _netc_tb_etmcq_update_action @@ -3092,7 +3130,7 @@ typedef struct _netc_tb_etmcs_cfge netc_tb_etmcs_ca_assg_t cqAssg : 4; /*!< Class Queue Assignment, input 0 to 7 are weighted fair whereby input 8 to 15 are strict priority */ uint32_t : 12; - uint32_t oal : 11; /*!< Overead accounting length */ + uint32_t oal : 11; /*!< Overead accounting length */ uint32_t : 5; struct { @@ -3142,7 +3180,7 @@ typedef struct _netc_tb_etmcs_config #endif /*! @brief ETM Congestion Group table entry ID macro, cgID is represents the Congestion Group ID ,rang in 0 ~ 7, portID * is Switch ID, rang in 0 ~ 4 */ -#define NETC_TB_ETM_CG_ENTRY_ID(portID, cgID) (((uint32_t)(portID) << 4U) | ((cgID)&0x7U)) +#define NETC_TB_ETM_CG_ENTRY_ID(portID, cgID) (((uint32_t)(portID) << 4U) | ((cgID) & 0x7U)) /*! @brief ETM Congestion Group table config element */ typedef struct _netc_tb_etmcg_cfge @@ -3157,7 +3195,7 @@ typedef struct _netc_tb_etmcg_cfge uint16_t tn : 5; /*!< TA */ uint16_t ta : 8; /*!< Tn */ uint16_t : 3; - } tdDRThresh[4]; /*!< Tail Drop Threshold (TA * 2^Tn) for DR0 ~ DR3 Frames, valid if tdDrnEn = 1b */ + } tdDRThresh[4]; /*!< Tail Drop Threshold (TA * 2^Tn) for DR0 ~ DR3 Frames, valid if tdDrnEn = 1b */ } netc_tb_etmcg_cfge_t; /*! @brief ETM Congestion Group table statistic element */ @@ -3248,7 +3286,7 @@ typedef struct _netc_tb_ec_data /*! @brief Buffer pool and shared buffer pool threshold macro, the threshold = MANT*2^EXP, uint is internal memory words * (avergae of 20 bytes each) */ -#define NETC_TB_BP_THRESH(mant, exp) (((uint32_t)((mant)&0xFF) << 4U) | ((exp)&0xF)) +#define NETC_TB_BP_THRESH(mant, exp) (((uint32_t)((mant) & 0xFF) << 4U) | ((exp) & 0xF)) /*! @brief Buffer Pool Flow Control (FC) Configuration */ typedef enum _netc_tb_bp_fc_cfg @@ -3267,23 +3305,23 @@ typedef struct _netc_tb_bp_cfge pool */ netc_tb_bp_fc_cfg_t gcCfg : 2; /*!< Flow Control (FC) Configuration */ uint8_t : 5; - uint8_t pfcVector; /*!< Priority Flow Control (PFC) Vector, not support in NETC 3.0 and 3.1 version */ - uint16_t maxThresh : 12; /*!< Maximum Threshold, value 0 means disable maximum threshold checking, use - NETC_TB_BP_THRESH macro to set this value */ + uint8_t pfcVector; /*!< Priority Flow Control (PFC) Vector, not support in NETC 3.0 and 3.1 version */ + uint16_t maxThresh : 12; /*!< Maximum Threshold, value 0 means disable maximum threshold checking, use + NETC_TB_BP_THRESH macro to set this value */ uint16_t : 4; - uint16_t fcOnThresh : 12; /*!< Flow Control On Threshold, If the buffer pool usage crosses this threshold, and if - fcOnThresh is greater than fcOffThresh, the flow control state of the buffer pool - is set to 1, use NETC_TB_BP_THRESH macro to set this value. */ + uint16_t fcOnThresh : 12; /*!< Flow Control On Threshold, If the buffer pool usage crosses this threshold, and if + fcOnThresh is greater than fcOffThresh, the flow control state of the buffer pool + is set to 1, use NETC_TB_BP_THRESH macro to set this value. */ uint16_t : 4; uint16_t fcOffThresh : 12; /*!< Flow Control Off Threshold, If buffer pool usage drops to this threshold or below, the flow control state of the buffer pool is set to 0, , use NETC_TB_BP_THRESH macro to set this value */ uint16_t : 4; - uint32_t sbpThresh : 12; /*!< Shared Buffer Pool Threshold, use NETC_TB_BP_THRESH macro to set this value */ + uint32_t sbpThresh : 12; /*!< Shared Buffer Pool Threshold, use NETC_TB_BP_THRESH macro to set this value */ uint32_t : 20; - uint32_t sbpEid; /*!< Shared Buffer Pool Entry ID, valid if sbpEn is true */ - uint32_t fcPorts; /*!< Flow Control Port bitmap, indicates which ports are to be flow controlled for this - buffer pool */ + uint32_t sbpEid; /*!< Shared Buffer Pool Entry ID, valid if sbpEn is true */ + uint32_t fcPorts; /*!< Flow Control Port bitmap, indicates which ports are to be flow controlled for this + buffer pool */ } netc_tb_bp_cfge_t; /*! @brief Buffer Pool table State Element Data*/ @@ -3343,12 +3381,12 @@ typedef struct _netc_tb_bp_config typedef struct _netc_tb_sbp_cfge { uint32_t : 16; - uint32_t maxThresh : 12; /*!< Maximum Threshold, If shared buffer pool usage is greater than or equal to this - threshold, use NETC_TB_BP_THRESH macro to set this value */ + uint32_t maxThresh : 12; /*!< Maximum Threshold, If shared buffer pool usage is greater than or equal to this + threshold, use NETC_TB_BP_THRESH macro to set this value */ uint32_t : 4; - uint16_t fcOnThresh : 12; /*!< Flow Control On Threshold, If the shared buffer pool usage crosses this threshold, - and if fcOnThresh is greater than fcOffThresh, the flow control state of the buffer pool - is set to 1, use NETC_TB_BP_THRESH macro to set this value. */ + uint16_t fcOnThresh : 12; /*!< Flow Control On Threshold, If the shared buffer pool usage crosses this threshold, + and if fcOnThresh is greater than fcOffThresh, the flow control state of the buffer pool + is set to 1, use NETC_TB_BP_THRESH macro to set this value. */ uint16_t : 4; uint16_t fcOffThresh : 12; /*!< Flow Control Off Threshold, If shared buffer pool usage drops to this threshold or below, the flow control state of the buffer pool is set to 0, use NETC_TB_BP_THRESH @@ -3444,7 +3482,7 @@ typedef union _netc_tb_data_buffer * @{ */ /*! @brief Macro to cover VLAN PCP, DEI value to internal used pcpDei value. */ -#define NETC_VLAN_PCP_DEI_VALUE(pcp, dei) (((uint8_t)((pcp)&0x7U) << 1U) | ((dei)&0x1U)) +#define NETC_VLAN_PCP_DEI_VALUE(pcp, dei) (((uint8_t)((pcp) & 0x7U) << 1U) | ((dei) & 0x1U)) /*! @brief VLAN Ethertypes. */ typedef enum _netc_hw_enetc_si_vlan_type @@ -3485,11 +3523,11 @@ typedef struct _netc_hw_enetc_si_config uint32_t ringPerBdrGroup : 3; /*!< The ring number in every Rx BD ring group, range in 1 ~ 8, active when rxBdrGroupNum not equal zero. */ netc_hw_enetc_si_rxr_group - defaultRxBdrGroup; /*!< The selected Rx BD ring group, active when rxBdrGroupNum not equal zero. */ + defaultRxBdrGroup; /*!< The selected Rx BD ring group, active when rxBdrGroupNum not equal zero. */ - uint8_t vlanToIpvMap[16]; /*!< Frame VLAN pcp|dei to IPV mapping, active when valnToIpvEnable is true. */ - uint8_t ipvToRingMap[8]; /*!< BD ring used within the default Rx BD ring group for IPV n, active when rxBdrGroupNum - not equal zero. */ + uint8_t vlanToIpvMap[16]; /*!< Frame VLAN pcp|dei to IPV mapping, active when valnToIpvEnable is true. */ + uint8_t ipvToRingMap[8]; /*!< BD ring used within the default Rx BD ring group for IPV n, active when rxBdrGroupNum + not equal zero. */ uint8_t vsiTcToTC[8]; /*!< Maps the VSI traffic class to transmit traffic class, done after the ENETC txPrio to TC mapping, only available for VSI. */ bool enSIBaseVlan; /*!< Enable use SI-based VLAN information. */ @@ -3565,24 +3603,40 @@ typedef union _netc_tx_bd uint32_t timestamp : 30; /*!< IEEE1588 PTP one-step timestamp. */ uint32_t : 2; /*!< Ignore 2-bit MSB. */ uint16_t : 14; - uint16_t tpid : 2; /*!< VLAN TPID type, see @ref netc_vlan_tpid_select_t. */ - uint16_t vid : 12; /*!< VLAN ID. */ - uint16_t dei : 1; /*!< VLAN DEI. */ - uint16_t pcp : 3; /*!< VLAN PCP. */ + uint16_t tpid : 2; /*!< VLAN TPID type, see @ref netc_vlan_tpid_select_t. */ + uint16_t vid : 12; /*!< VLAN ID. */ + uint16_t dei : 1; /*!< VLAN DEI. */ + uint16_t pcp : 3; /*!< VLAN PCP. */ +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG + uint32_t lsoMaxSegSize : 14; + uint32_t : 2; + uint32_t frameLenExt : 4; + uint32_t : 12; +#else uint32_t : 32; +#endif uint16_t : 16; - uint8_t eFlags; /*!< Tx extension flags. */ + uint8_t eFlags; /*!< Tx extension flags. */ uint8_t : 7; uint8_t isFinal : 1; /*!< Final BD flag. */ } ext; struct { - uint32_t timestamp; /*!< Timestamp write back. */ + uint32_t timestamp; /*!< Timestamp write back. */ +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG + uint32_t : 32; +#else uint32_t txtsid : 16; /*!/ Transmit timestamp identifier, only active on Switch management ENETC. */ uint32_t : 16; +#endif uint32_t : 32; +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG + uint32_t lsoErrCnt : 4; + uint32_t : 12; +#else uint32_t : 16; - uint32_t status : 9; /*!< Status. */ +#endif + uint32_t status : 9; /*!< Status. */ uint32_t : 1; uint32_t written : 1; /*!< Write-back flag. */ uint32_t : 5; @@ -3608,24 +3662,24 @@ typedef union _netc_rx_bd { struct { - uint32_t srcPort : 5; /*!< Source port received from switch management port. */ + uint32_t srcPort : 5; /*!< Source port received from switch management port. */ uint32_t : 3; uint32_t rssHash : 24; /*!< RSS Hash high field value. */ }; - uint32_t rssHashSwt; /*!< RSS hash while not used as switch management port. */ + uint32_t rssHashSwt; /*!< RSS hash while not used as switch management port. */ }; - uint16_t bufLen; /*!< Length of received buffer. */ - uint16_t vid : 12; /*!< VLAN ID. */ - uint16_t dei : 1; /*!< VLAN DEI. */ - uint16_t pcp : 3; /*!< VLAN PCP. */ - uint8_t tpid : 2; /*!< VLAN TPID. */ - uint8_t hr : 4; /*!< Host Reason. */ + uint16_t bufLen; /*!< Length of received buffer. */ + uint16_t vid : 12; /*!< VLAN ID. */ + uint16_t dei : 1; /*!< VLAN DEI. */ + uint16_t pcp : 3; /*!< VLAN PCP. */ + uint8_t tpid : 2; /*!< VLAN TPID. */ + uint8_t hr : 4; /*!< Host Reason. */ uint8_t : 2; - uint8_t flags; /*!< Rx information flags. */ - uint8_t error; /*!< Rx error code. */ + uint8_t flags; /*!< Rx information flags. */ + uint8_t error; /*!< Rx error code. */ uint8_t : 6; - uint8_t isReady : 1; /*!< Received data ready flag. */ - uint8_t isFinal : 1; /*!< Final BD flag. */ + uint8_t isReady : 1; /*!< Received data ready flag. */ + uint8_t isFinal : 1; /*!< Final BD flag. */ } writeback; struct { @@ -3633,20 +3687,22 @@ typedef union _netc_rx_bd uint32_t : 32; uint64_t : 64; } ext; +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) struct { uint32_t timestamp; /*!< Switch response timestamp. */ uint32_t : 32; - uint16_t txtsid; /*!< Transmit timestamp identifier. */ + uint16_t txtsid; /*!< Transmit timestamp identifier. */ uint16_t : 16; uint32_t : 2; - uint32_t hr : 4; /*!< Host Reason. */ + uint32_t hr : 4; /*!< Host Reason. */ uint32_t : 10; - uint32_t error : 8; + uint32_t error : 8; /*!< Error status code. */ uint32_t : 6; uint32_t isReady : 1; /*!< Received data ready flag. */ uint32_t isFinal : 1; /*!< Final BD flag. */ } resp; +#endif } netc_rx_bd_t; /*! @brief Configuration for the SI Tx Buffer Descriptor Ring Configuration. */ @@ -3981,6 +4037,17 @@ typedef struct _netc_switch_inuse_fdb_statistic uint16_t dynamicEntriesHWM; /*!< High water mark of dynamic entries in-use in the FDB table. */ } netc_switch_inuse_fdb_statistic_t; +/*! @brief Port seamless redundancy configuration */ +typedef struct _netc_swt_port_sr_config +{ + uint16_t isqEID; + uint8_t pathId; + bool txSqta; + bool srcPortFlt; + bool sdfa; + bool srPort; +} netc_swt_port_sr_config_t; + /*! @} */ // end of netc_hw_switch #if !(defined(__GNUC__) || defined(__ICCARM__)) #pragma endregion netc_hw_switch diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c index 1dd7a424f1..0df1859aa9 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c @@ -1,5 +1,5 @@ /* - * Copyright 2021-2024 NXP + * Copyright 2021-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,8 +15,8 @@ /*! @name Defines some Ethernet parameters. */ /*@{*/ -#define NETC_ENETC_TXFRAME_LEN_MAX (9600U) /*!< The Maximum length of frame length. */ -#define NETC_ENETC_TXFRAME_LEN_MIN (16U) /*!< The Minimum length of frame length. */ +#define NETC_ENETC_TXFRAME_LEN_MAX (9600U) /*!< The Maximum length of frame length. */ +#define NETC_ENETC_TXFRAME_LEN_MIN (16U) /*!< The Minimum length of frame length. */ /*@}*/ /*! @brief Mask the cache management code if cache control is disabled. */ @@ -188,12 +188,14 @@ static status_t EP_DescriptorInit(ep_handle_t *handle, const ep_config_t *config uint8_t idxStart = 0U; uint8_t ring; +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) /* Setup Tx/Rx buffer descriptor rings. */ if (NETC_EnetcHasManagement(handle->hw.base) && (getSiNum(handle->cfg.si) == 0U)) { /* For management ENETC, the SI 0 hardware Tx ring index 0 has been keep for direct switch enqueue feature */ idxStart = 1; } +#endif for (ring = 0; ring < config->siConfig.txRingUse; ring++) { if (NETC_SIConfigTxBDR(handle->hw.si, ring + idxStart, &bdrConfig->txBdrConfig[ring]) != kStatus_Success) @@ -332,8 +334,9 @@ static status_t EP_MSIXSetEntryTable(ep_handle_t *handle, const ep_config_t *con return result; } - msixNum = (uint8_t)( - ((handle->hw.si->SIPCAPR1 & ENETC_SI_SIPCAPR1_NUM_MSIX_MASK) >> ENETC_SI_SIPCAPR1_NUM_MSIX_SHIFT) + 1U); + msixNum = + (uint8_t)(((handle->hw.si->SIPCAPR1 & ENETC_SI_SIPCAPR1_NUM_MSIX_MASK) >> ENETC_SI_SIPCAPR1_NUM_MSIX_SHIFT) + + 1U); /* Entry > 0, enable MSIX. */ if (config->entryNum != 0U) @@ -423,27 +426,28 @@ status_t EP_GetDefaultConfig(ep_config_t *config) #if (defined(FSL_FEATURE_NETC_HAS_PORT_FCSEA) && FSL_FEATURE_NETC_HAS_PORT_FCSEA) config->port.common.stompFcs = true; #endif - config->port.common.rxPpduBco = 20U; - config->port.common.txPpduBco = 20U; - config->port.common.timeGate.holdSkew = 64; - config->port.common.parser.l2PloadCount = 24; - config->port.common.parser.l3PayloadCount = 24; - config->port.common.parser.enableL3Parser = true; - config->port.common.parser.l4PayloadCount = 24; - config->port.common.parser.enableL4Parser = true; - config->port.ethMac.enableRevMii = false; - config->port.ethMac.preemptMode = kNETC_PreemptDisable; - config->port.ethMac.enMergeVerify = false; - config->port.ethMac.mergeVerifyTime = 10U; - config->port.ethMac.txTsSelect = kNETC_SyncTime; - config->port.ethMac.enTxPad = true; - config->port.ethMac.rxMinFrameSize = 64U; - config->port.ethMac.rxMaxFrameSize = 0x600U; - config->port.ethMac.maxBackPressOn = 3036U; - config->port.ethMac.minBackPressOff = 20U; - config->port.enPseudoMacTxPad = true; - config->psfpCfg.isiPortConfig.defaultISEID = 0xFFFFU; - config->siConfig.ringPerBdrGroup = 0x1U; + config->port.common.rxPpduBco = 20U; + config->port.common.txPpduBco = 20U; + config->port.common.timeGate.holdSkew = 64; + config->port.common.parser.l2PloadCount = 24; + config->port.common.parser.l3PayloadCount = 24; + config->port.common.parser.enableL3Parser = true; + config->port.common.parser.l4PayloadCount = 24; + config->port.common.parser.enableL4Parser = true; + config->port.ethMac.enableRevMii = false; + config->port.ethMac.txTsSelect = kNETC_SyncTime; + config->port.ethMac.enTxPad = true; + config->port.ethMac.rxMinFrameSize = 64U; + config->port.ethMac.rxMaxFrameSize = 0x600U; + config->port.ethMac.maxBackPressOn = 3036U; + config->port.ethMac.minBackPressOff = 20U; + config->port.ethMac.PreemptionConfig.preemptMode = kNETC_PreemptDisable; + config->port.ethMac.PreemptionConfig.enMergeVerify = false; + config->port.ethMac.PreemptionConfig.mergeVerifyTime = 10U; + config->port.ethMac.PreemptionConfig.raf_size = kNETC_RafSize64; + config->port.enPseudoMacTxPad = true; + config->psfpCfg.isiPortConfig.defaultISEID = 0xFFFFU; + config->siConfig.ringPerBdrGroup = 0x1U; for (uint8_t i = 0U; i < 8U; i++) { config->txTcCfg[i].enTcGate = true; @@ -668,9 +672,9 @@ status_t EP_Init(ep_handle_t *handle, uint8_t *macAddr, const ep_config_t *confi return result; } - if (siNum == 0U) + if (siNum == 0U && config->preinitVsi != NULL) { - result = NETC_SocPreInitVsi(&handle->hw, config->si); + result = config->preinitVsi(&handle->hw, config->si); } return result; } @@ -718,9 +722,10 @@ status_t EP_Down(ep_handle_t *handle) NETC_EnetcEnableSI(handle->hw.base, getSiNum(handle->cfg.si), false); NETC_SIEnable(handle->hw.si, false); #if defined(FSL_FEATURE_NETC_HAS_ERRATA_051936) && FSL_FEATURE_NETC_HAS_ERRATA_051936 - /* ERRATA051936: MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. In some cases, the transmitter - may become inoperable and not be able to recover from FLR requiring a full reset instead. The issue can occur when FLR is triggered around - the time MAC Tx has started backing off due to a half duplex collision detection. */ + /* ERRATA051936: MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. In some + cases, the transmitter may become inoperable and not be able to recover from FLR requiring a full reset instead. + The issue can occur when FLR is triggered around the time MAC Tx has started backing off due to a half duplex + collision detection. */ handle->hw.portGroup.eth->PM0_IF_MODE &= ~NETC_ETH_LINK_PM0_IF_MODE_HD_MASK; handle->hw.portGroup.eth->PM1_IF_MODE &= ~NETC_ETH_LINK_PM0_IF_MODE_HD_MASK; #endif @@ -759,12 +764,12 @@ status_t EP_SendFrameCommon(ep_handle_t *handle, status_t result = kStatus_Success; netc_buffer_struct_t *txBuff = frame->buffArray; uint32_t totBdNum = frame->length; - uint16_t frameLen = 0; + uint32_t frameLen = 0; bool isExtEnable = (bool)txDesc[0].standard.isExtended; - uint32_t address; netc_tx_bd_t *txDesTemp = NULL; + uint32_t address; - /* Check the frame length. */ + /* The first descriptor in a chain must not have a BUFF_LEN that is less than 16 bytes. */ if ((frame->buffArray[0].length < NETC_ENETC_TXFRAME_LEN_MIN) || (frame->length == 0U)) { result = kStatus_NETC_TxFrameOverLen; @@ -787,7 +792,7 @@ status_t EP_SendFrameCommon(ep_handle_t *handle, } /* Check the frame total length. */ - if ((frameLen > NETC_ENETC_TXFRAME_LEN_MAX) || (frameLen < NETC_ENETC_TXFRAME_LEN_MIN)) + if (frameLen > NETC_ENETC_TXFRAME_LEN_MAX) { result = kStatus_NETC_TxFrameOverLen; } @@ -825,6 +830,7 @@ status_t EP_SendFrameCommon(ep_handle_t *handle, { /* Update latest Tx dirty frame info. */ txBdRing->dirtyBase[txBdRing->producerIndex].context = context; +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) if (0U != (txDesc[0].standard.flags & NETC_SI_TXDESCRIP_RD_TSR_MASK)) { txBdRing->dirtyBase[txBdRing->producerIndex].isTxTsIdAvail = true; @@ -833,6 +839,7 @@ status_t EP_SendFrameCommon(ep_handle_t *handle, { txBdRing->dirtyBase[txBdRing->producerIndex].isTxTsIdAvail = false; } +#endif if (isExtEnable && (0U != (txDesc[1].ext.eFlags & (uint32_t)kNETC_TxExtTwoStepTs))) { @@ -843,10 +850,15 @@ status_t EP_SendFrameCommon(ep_handle_t *handle, txBdRing->dirtyBase[txBdRing->producerIndex].isTsAvail = false; } /* Copy user Tx descriptors to hardware Tx BD. */ - txDesTemp->standard.flags = txDesc[0].standard.flags; - txDesTemp->standard.addr = address; - txDesTemp->standard.bufLen = txBuff->length; - txDesTemp->standard.frameLen = frameLen; + txDesTemp->standard.flags = txDesc[0].standard.flags; + txDesTemp->standard.addr = address; + txDesTemp->standard.bufLen = txBuff->length; +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG + txDesc[1].ext.frameLenExt = (frameLen >> 16U) & 0x7U; + txDesTemp->standard.frameLen = frameLen & 0xFFFFU; +#else + txDesTemp->standard.frameLen = frameLen; +#endif txDesTemp->standard.isExtended = (uint32_t)isExtEnable; txDesTemp->standard.enableInterrupt = (uint32_t)((handle->hw.si->BDR[hwRing].TBIER & ENETC_SI_TBIER_TXFIE_MASK) != 0U); @@ -897,12 +909,15 @@ status_t EP_SendFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *fr /* Tx BD ring index is out of range */ return kStatus_InvalidArgument; } + +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) if (NETC_EnetcHasManagement(handle->hw.base) && (getSiNum(handle->cfg.si) == 0U)) { /* Switch management ENETC Tx BD hardware ring 0 can't be used to send regular frame, so the index need increase * 1 */ hwRing = ring + 1U; } +#endif if (opt != NULL) { @@ -911,6 +926,18 @@ status_t EP_SendFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *fr txDesc[0].standard.flags = NETC_SI_TXDESCRIP_RD_FL(0x2U) | NETC_SI_TXDESCRIP_RD_TSE_MASK | NETC_SI_TXDESCRIP_RD_TXSTART(opt->timestamp); } +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG + else + { + txDesc[0].standard.flags = + NETC_SI_TXDESCRIP_RD_LSO(opt->offload.lso) | NETC_SI_TXDESCRIP_RD_L4CS(opt->offload.l4Checksum) | + NETC_SI_TXDESCRIP_RD_L4T(opt->offload.l4Type) | NETC_SI_TXDESCRIP_RD_L3T(opt->offload.l3Type) | + NETC_SI_TXDESCRIP_RD_L3HDRSIZE(opt->offload.l3HeaderSize) | + NETC_SI_TXDESCRIP_RD_IPCS(opt->offload.ipv4Checksum) | + NETC_SI_TXDESCRIP_RD_L3START(opt->offload.l3Start); + } +#endif + if ((opt->flags & (uint32_t)kEP_TX_OPT_VLAN_INSERT) != 0U) { txDesc[0].standard.isExtended = 1U; @@ -978,10 +1005,12 @@ netc_tx_frame_info_t *EP_ReclaimTxDescCommon(ep_handle_t *handle, { frameInfo->timestamp = txDesc->writeback.timestamp; } +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) if (frameInfo->isTxTsIdAvail) { frameInfo->txtsid = (uint16_t)txDesc->writeback.txtsid; } +#endif frameInfo->status = (netc_ep_tx_status_t)txDesc->writeback.status; } else if (txDesc->standard.frameLen != 0U) @@ -1027,13 +1056,14 @@ void EP_ReclaimTxDescriptor(ep_handle_t *handle, uint8_t ring) netc_tx_frame_info_t *frameInfo; uint8_t hwRing = ring; +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) if (NETC_EnetcHasManagement(handle->hw.base) && (getSiNum(handle->cfg.si) == 0U)) { /* Switch management ENETC Tx BD hardware ring 0 can't be used to send regular frame, so the index need increase * 1 */ hwRing = ring + 1U; } - +#endif do { frameInfo = @@ -2140,7 +2170,7 @@ status_t EP_TxTGSConfigAdminGcl(ep_handle_t *handle, netc_tb_tgs_gcl_t *config) uint64_t time, minBaseTime; /* Read the previous active Operationa gate control list cycle time*/ - (void)memset(cdbrHandle.buffer, 0, sizeof(netc_tb_tgs_data_t)); + (void)memset(cdbrHandle.buffer, 0, sizeof(netc_tb_tgs_req_data_t)); cdbrHandle.buffer->tgs.request.entryID = config->entryID; cdbrHandle.buffer->tgs.request.commonHeader.updateActions = 0U; cdbrHandle.buffer->tgs.request.commonHeader.queryActions = 0U; diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.h index 7debcfb070..7dba6f74d9 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.h +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.h @@ -1,5 +1,5 @@ /* - * Copyright 2021-2024 NXP + * Copyright 2021-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -179,20 +179,42 @@ typedef enum _ep_rx_flags typedef enum _ep_tx_opt_flags { - kEP_TX_OPT_REQ_TS = 0x1U, /*!< Request timestamp (IEEE 1588 PTP two-step timestamp). */ - kEP_TX_OPT_VLAN_INSERT = 0x2U, /*!< Enable VLAN insert. */ - kEP_TX_OPT_START_TIME = 0x4U, /*!< Specifiy frame departure time. */ + kEP_TX_OPT_REQ_TS = 0x1U, /*!< Request timestamp (IEEE 1588 PTP two-step timestamp). */ + kEP_TX_OPT_VLAN_INSERT = 0x2U, /*!< Enable VLAN insert. */ + kEP_TX_OPT_START_TIME = 0x4U, /*!< Specifiy frame departure time. */ #if !(defined(FSL_FEATURE_NETC_HAS_ERRATA_051255) && FSL_FEATURE_NETC_HAS_ERRATA_051255) kEP_TX_OPT_REQ_ONE_STEP_TS = 0x8U, /*!< Request IEEE 1588 PTP one-step timestamp offload. */ #endif } ep_tx_opt_flags; +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) typedef struct _ep_tx_opt { uint32_t flags; /*!< A bitmask of ep_tx_opt_flags */ uint32_t timestamp; /*!< Departure timestamp, used if kEP_TX_OPT_START_TIME is set */ netc_enetc_vlan_tag_t vlan; /*!< VLAN tag which will be inserted, used if kEP_TX_OPT_VLAN_INSERT is set */ } ep_tx_opt; +#else +typedef struct _ep_tx_offload +{ + bool lso; /*!< Large send offload. */ + bool l4Checksum; /*!< L4 checksum offload. */ + bool ipv4Checksum; /*!< IPv4 checksum offload. */ + uint32_t lsoMaxSegSize : 14; /*!< Large send offload maximum segment size. */ + uint32_t l4Type : 3; /*!< L4 type. 1-UDP, 2-TCP. */ + uint32_t l3Type : 1; /*!< L3 type. 0-IPv4, 1-IPv6. */ + uint32_t l3HeaderSize : 7; /*!< L3 IP header size in units of 32-bit words. */ + uint32_t l3Start : 7; /*!< Offset of the IPv4/IPv6 header in units of bytes. */ +} netc_tx_offload_t; + +typedef struct _ep_tx_opt +{ + uint32_t flags; /*!< A bitmask of ep_tx_opt_flags */ + uint32_t timestamp; /*!< Departure timestamp, used if kEP_TX_OPT_START_TIME is set */ + netc_enetc_vlan_tag_t vlan; /*!< VLAN tag which will be inserted, used if kEP_TX_OPT_VLAN_INSERT is set */ + netc_tx_offload_t offload; +} ep_tx_opt; +#endif /*! @} */ // end of netc_ep_xfer #if !(defined(__GNUC__) || defined(__ICCARM__)) @@ -247,7 +269,12 @@ typedef void (*ep_rx_free_cb_t)(ep_handle_t *handle, uint8_t ring, void *address typedef status_t (*ep_get_link_status_cb_t)(ep_handle_t *handle, uint8_t *link); /*! @brief Callback for getting link speed */ -typedef status_t (*ep_get_link_speed_cb_t)(ep_handle_t *handle, netc_hw_mii_speed_t *speed, netc_hw_mii_duplex_t *duplex); +typedef status_t (*ep_get_link_speed_cb_t)(ep_handle_t *handle, + netc_hw_mii_speed_t *speed, + netc_hw_mii_duplex_t *duplex); + +/*! @brief Callback for vsi pre-init */ +typedef status_t (*ep_preinit_vsi_cb_t)(netc_enetc_hw_t *hw, netc_hw_si_idx_t si); /*! @brief Configuration for the endpoint handle. */ typedef struct _ep_config @@ -284,6 +311,7 @@ typedef struct _ep_config bool rxZeroCopy; /*!< Enable/Disable zero-copy receive mode. */ ep_rx_alloc_cb_t rxBuffAlloc; /*!< Callback function to alloc memory, must be provided for zero-copy Rx. */ ep_rx_free_cb_t rxBuffFree; /*!< Callback function to free memory, must be provided for zero-copy Rx. */ + ep_preinit_vsi_cb_t preinitVsi; /*!< Callback function to pre-init VSI */ netc_cmd_bdr_config_t cmdBdrConfig; /*!< Command BD ring configuration. */ } ep_config_t; @@ -1194,6 +1222,75 @@ status_t EP_TxtTGSGetOperGcl(ep_handle_t *handle, netc_tb_tgs_gcl_t *gcl, uint32 */ status_t EP_TxTrafficClassConfig(ep_handle_t *handle, netc_hw_tc_idx_t tcIdx, const netc_port_tx_tc_config_t *config); +/*! + * @brief Config Preemption for each port TC (traffic class) + * + * @param handle + * @param tcIdx + * @param enable + */ +static inline void EP_TxTcConfigPreemption(ep_handle_t *handle, netc_hw_tc_idx_t tcIdx, const bool enable) +{ + NETC_PORT_Type *base; + + base = handle->hw.portGroup.port; + if (!NETC_PortIsPseudo(base)) + { + NETC_PortConfigTcPreemption(base, tcIdx, enable); + } +} + +/*! + * @brief Get Preemption configuration for each port TC (traffic class) + * + * @param handle + * @param tcIdx + * @param enabled + */ +static inline void EP_TxGetTcPreemption(ep_handle_t *handle, netc_hw_tc_idx_t tcIdx, bool *enabled) +{ + NETC_PORT_Type *base; + + base = handle->hw.portGroup.port; + if (!NETC_PortIsPseudo(base)) + { + NETC_PortGetTcPreemption(base, tcIdx, enabled); + } +} + +/*! + * @brief Configure Preemption control configuration for an ethernet MAC + * + * @param handle + * @param config + */ +static inline void EP_TxPortEthMacConfigPreemption(ep_handle_t *handle, const netc_port_preemption_config *config) +{ + NETC_ETH_LINK_Type *base; + + base = handle->hw.portGroup.eth; + NETC_PortConfigEthMacPreemption(base, config); +} + +/*! + * @brief Get Preemption configuration from ethernet MAC port + * + * @param handle + * @param config + * @param status + */ +static inline void EP_TxPortGetEthMacPreemption(ep_handle_t *handle, + netc_port_preemption_config *config, + netc_port_phy_mac_preemption_status_t *status) +{ + NETC_ETH_LINK_Type *base; + + base = handle->hw.portGroup.eth; + NETC_PortGetPhyMacPreemptionControl(base, config); + + NETC_PortGetPhyMacPreemptionStatus(base, status); +} + /*! @} */ // end of netc_ep_tx #if !(defined(__GNUC__) || defined(__ICCARM__)) #pragma endregion netc_ep_tx @@ -1380,12 +1477,14 @@ status_t EP_SendFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *fr static inline void EP_WaitUnitilTxComplete(ep_handle_t *handle, uint8_t ring) { uint8_t hwRing = ring; +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) if (NETC_EnetcHasManagement(handle->hw.base) && (getSiNum(handle->cfg.si) == 0U)) { /* Switch management ENETC Tx BD hardware ring 0 can't be used to send regular frame, so the index need increase * 1 */ hwRing++; } +#endif while (handle->hw.si->BDR[hwRing].TBCIR != handle->txBdRing[ring].producerIndex) { } diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_ierb.c b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_ierb.c index 272e3a1dc6..6647256e9c 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_ierb.c +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_ierb.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,5 +39,3 @@ status_t NETC_IERBUnlock(void) return kStatus_Success; } - - diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_ierb.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_ierb.h index 653447550f..c0b2b4a4c5 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_ierb.h +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_ierb.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,7 +11,8 @@ /*! * @brief Software reset NETC module - * Software should follow these steps when initiating a soft reset to avoid hanging any outstanding transactions in the system. + * Software should follow these steps when initiating a soft reset to avoid hanging any outstanding transactions in the + * system. * - Software disables MAC receive function(s). * - Software sets the soft reset bit NETCRR[SR]=1. * + NETC stops further prefetching of BDs @@ -19,7 +20,8 @@ * - Software waits for NETC to complete any in-flight transmit frames processing. * + If there is use of time gating or credit based shaping, worst case wait time is SaTGSLR/EaTGSLR[MIN_LOOKAHEAD] + * PTGSATOR[ADV_TIME_OFFSET] + Transmit(MAX_SDU) + Writeback BD. - * + If there is no use of time gating or credit based shaping, worst case wait time is Transmit(MAX_SDU) + Writeback BD. + * + If there is no use of time gating or credit based shaping, worst case wait time is Transmit(MAX_SDU) + Writeback + * BD. * - Software waits for either: * + 100 ms (as per PCIe specification). * + Shortest possible reset time as defined by IERB register NETCFLRCR. diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_mdio.c b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_mdio.c index da34a75f9d..893d59efa9 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_mdio.c +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_mdio.c @@ -1,5 +1,5 @@ /* - * Copyright 2021-2022 NXP + * Copyright 2021-2022, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -258,8 +258,7 @@ static void NETC_PIMDIO_C45Write( NETC_ETH_LINK_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data) { base->PM0_MDIO_CFG |= NETC_ETH_LINK_PM0_MDIO_CFG_ENC45_MASK; - base->PM0_MDIO_CTL = NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR(portAddr) | - NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR(devAddr); + base->PM0_MDIO_CTL = NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR(portAddr) | NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR(devAddr); base->PM0_MDIO_ADDR = NETC_ETH_LINK_PM0_MDIO_ADDR_REGADDR(regAddr); while (NETC_PIMDIO_IsSMIBusy(base)) @@ -276,8 +275,7 @@ static status_t NETC_PIMDIO_C45Read( NETC_ETH_LINK_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData) { base->PM0_MDIO_CFG |= NETC_ETH_LINK_PM0_MDIO_CFG_ENC45_MASK; - base->PM0_MDIO_CTL = NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR(portAddr) | - NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR(devAddr); + base->PM0_MDIO_CTL = NETC_ETH_LINK_PM0_MDIO_CTL_PORT_ADDR(portAddr) | NETC_ETH_LINK_PM0_MDIO_CTL_DEV_ADDR(devAddr); base->PM0_MDIO_ADDR = NETC_ETH_LINK_PM0_MDIO_ADDR_REGADDR(regAddr); while (NETC_PIMDIO_IsSMIBusy(base)) diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.c b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.c index ce40f80d98..97beeb8037 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.c +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.c @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -233,9 +233,9 @@ static uint16_t EP_RxL2MFQueryDeleteEMTableEntry(ep_handle_t *handle, uint8_t si } else { - m = 6U * i; + m = 6U * i; cmdBd.generic.addr = ((uint64_t)macAddr[m + 4U] << 32U) + ((uint64_t)macAddr[m + 5U] << 40U) + - *(uint32_t *)(uintptr_t)&macAddr[m]; + *(uint32_t *)(uintptr_t)&macAddr[m]; } cmdBd.generic.addr = 0; @@ -1058,7 +1058,7 @@ void EP_PsiHandleRxMsg(ep_handle_t *handle, uint8_t vsi, netc_psi_rx_msg_t *msgI ENETC_SI_Type *base = handle->hw.si; bool notify = false; uint32_t crc; - hal_crc_config_t config = { + hal_crc_config_t config = { .crcSize = 2U, .crcStartByte = 2U, .crcRefIn = KHAL_CrcInputNoRef, diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.h index a7c97c9974..6af7772f5d 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.h +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_msg.h @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,8 @@ #include "fsl_netc.h" #include "fsl_netc_endpoint.h" -#define NETC_MSG_RETURN_CODE(class, code, cookie) (((uint16_t)(class) << 8U) | ((uint16_t)(code) << 4U) | (uint16_t)(cookie)) +#define NETC_MSG_RETURN_CODE(class, code, cookie) \ + (((uint16_t)(class) << 8U) | ((uint16_t)(code) << 4U) | (uint16_t)(cookie)) /*! * @brief VSI-PSI message class id diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_phy_wrapper.c b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_phy_wrapper.c index 811e124f07..b0c1c56ebc 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_phy_wrapper.c +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_phy_wrapper.c @@ -6,8 +6,7 @@ #include "fsl_netc_phy_wrapper.h" -static void NETC_PHYWriteRegBits( - netc_mdio_handle_t *handle, bool pcs, volatile uint16_t *reg, uint16_t mask, uint16_t val) +status_t NETC_PHYWriteRegBits(netc_mdio_handle_t *handle, bool pcs, volatile uint16_t *reg, uint16_t mask, uint16_t val) { uint8_t portAddr = pcs ? 0x0U : 0x10U; uint8_t devAddr = getPhyDev(reg); @@ -16,7 +15,10 @@ static void NETC_PHYWriteRegBits( status_t status; status = NETC_MDIOC45Read(handle, portAddr, devAddr, regAddr, ®Value); - assert(status == kStatus_Success); + if (status != kStatus_Success) + { + return status; + } regValue &= ~mask; if (val != 0U) @@ -24,553 +26,14 @@ static void NETC_PHYWriteRegBits( regValue |= val; } - status = NETC_MDIOC45Write(handle, portAddr, devAddr, regAddr, regValue); - if (status != kStatus_Success) - { - assert(false); - } + return NETC_MDIOC45Write(handle, portAddr, devAddr, regAddr, regValue); } -static void NETC_PHYReadReg(netc_mdio_handle_t *handle, bool pcs, const volatile uint16_t *reg, uint16_t *val) +status_t NETC_PHYReadReg(netc_mdio_handle_t *handle, bool pcs, const volatile uint16_t *reg, uint16_t *val) { uint8_t portAddr = pcs ? 0x0U : 0x10U; uint8_t devAddr = getPhyDev(reg); uint16_t regAddr = getPhyReg(reg); - status_t status; - - status = NETC_MDIOC45Read(handle, portAddr, devAddr, regAddr, val); - if (status != kStatus_Success) - { - assert(false); - } -} - -status_t NETC_PHYInit(netc_mdio_handle_t *handle, phy_mode_t mode) -{ - uint16_t regValue; - -#if !(defined(FSL_FEATURE_NETC_HAS_NO_XGMII) && FSL_FEATURE_NETC_HAS_NO_XGMII) - if ((mode == kNETC_XGMII10G) || (mode == kNETC_XGMII10GAuto)) - { - NETC_PHYWriteRegBits(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_PHY, - ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_MASK, - ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK(0x1U)); - NETC_PHYWriteRegBits(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_MPLLA, - ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_MASK, - ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK(0x1U)); - NETC_PHYWriteRegBits(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_MPLLB, - ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_MASK, - ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK(0x1U)); - NETC_PHYWriteRegBits(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_RAM, - ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_MASK, - ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK(0x1U)); - NETC_PHYWriteRegBits(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_ROM, - ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_MASK, - ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_SRAM, ®Value); - regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN_MASK; - } while (regValue == 0x0U); - NETC_PHYWriteRegBits(handle, false, &ENET_PHY_CTRL_EX->GLOBAL_CTRL_EX_0, - ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS_MASK, - ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_XS_PCS_MMD->SR_XS_PCS_CTRL1, ®Value); - regValue &= ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_RST_MASK; - } while (regValue != 0x0U); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, - ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE_MASK, - ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x1U)); - SDK_DelayAtLeastUs(1, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE(0x3U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x3U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, ®Value); - regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK; - } while (regValue != 0x0U); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value); - regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK; - } while (regValue != 0x0U); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RANGE_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RANGE(0x6U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_DIV2_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_DIV2(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV2_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV2(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_TX_CLK_DIV(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_CLK_EN_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_CLK_EN(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_MULT_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_MULT(0x5U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_EN_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_EN(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL5, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL4, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL5, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_SPD_EN_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_SPD_EN(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_FRACN_CTRL_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_FRACN_CTRL(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER(0x21U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_LVL_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_LVL(0x5U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL3, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX_VREF_CTRL_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX_VREF_CTRL(0x11U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_MISC_CTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_SUP_MISC_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_SUP_MISC(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0(0x29U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0(0x549U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0_RX0_CDR_PPM_MAX_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0_RX0_CDR_PPM_MAX(0x12U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0_TX0_MISC_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0_TX0_MISC(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLLB_SEL_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLLB_SEL_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH(0x3U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL_TX0_IBOOST_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL_TX0_IBOOST(0xFU)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_PRE_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_PRE(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1_TX_EQ_POST_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1_TX_EQ_POST(0x20U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_MAIN_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_MAIN(0x20U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_POLE_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_POLE_0(0x2U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0(0x10U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL3, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_TRSHLD_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_TRSHLD_0(0x7U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC(0x12U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH(0x3U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL_CDR_SSC_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL_CDR_SSC_EN_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL3, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_LFPS_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_LFPS_EN_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_GENCTRL4, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL_RX0_EQ_ATT_LVL_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL_RX0_EQ_ATT_LVL(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA1_GAIN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA1_GAIN_0(0x5U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA2_GAIN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA2_GAIN_0(0x5U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0_DFE_TAP1_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0_DFE_TAP1_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_TERM_ACDC_0_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_TERM_ACDC_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_SEL_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_SEL_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE(0x3U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->SR_XS_PCS_CTRL2, - ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL_MASK, - ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USXG_EN_MASK, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USXG_EN(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_KR_CTRL, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_MODE_MASK, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_MODE(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->SR_XS_PCS_CTRL2, - ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL_MASK, - ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER(0x21U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL3, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0(0x549U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0(0x29U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_ADAPT_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_ADAPT_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH(0x3U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH(0x3U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0(0x10U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC(0x12U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_GENCTRL4, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE(0x3U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST_MASK, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_SRAM, ®Value); - regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN_MASK; - } while (regValue == 0x0U); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_SRAM, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_EXT_LD_DN_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_EXT_LD_DN(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, ®Value); - regValue &= ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST_MASK; - } while (regValue != 0x0U); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value); - regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK; - } while (regValue != 0x0U); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DEBUG_CTRL, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_LOS_DET_MASK, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_LOS_DET(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DEBUG_CTRL, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_DT_EN_CTL_MASK, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_DT_EN_CTL(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_RX_LSTS, ®Value); - regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_0_MASK; - } while (regValue == 0x0U); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MISC_STS, ®Value); - regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RX_ADPT_ACK_MASK; - } while (regValue == 0x0U); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ(0x0U)); - - if (mode == kNETC_XGMII10GAuto) - { - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_CTRL, - ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_AN_INTR_EN_MASK, - ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_AN_INTR_EN(0x1U)); - } - - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_CTRL, - ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_TX_CONFIG_MASK, - ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_TX_CONFIG(0x0U)); - - if (mode == kNETC_XGMII10GAuto) - { - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_LINK_TIMER_CTRL, - ENET_PHY_VS_MII_MMD_VR_MII_LINK_TIMER_CTRL_CL37_LINK_TIME_MASK, - ENET_PHY_VS_MII_MMD_VR_MII_LINK_TIMER_CTRL_CL37_LINK_TIME(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_DIG_CTRL1, - ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_MASK, - ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE(0x1U)); - } - - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS6_MASK, - ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS6(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS13_MASK, - ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS13(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS5_MASK, - ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS5(0x0U)); - - NETC_PHYWriteRegBits(handle, true, &ENET_PHY->LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0, - ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE_MASK, - ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE(0x169U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY->LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0, - ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN_MASK, - ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY->LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2, - ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK_MASK, - ENET_PHY_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK(0x1U)); - - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DEBUG_CTRL, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_TX_PMBL_CTL_MASK, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_TX_PMBL_CTL(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE(0x2U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, ®Value); - regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK; - } while (regValue != 0x0U); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value); - regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK; - } while (regValue != 0x0U); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX_DISABLE_0_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX_DISABLE_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK, - ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x0U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0(0x1U)); - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK, - ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, ®Value); - regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK; - } while (regValue != 0x0U); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value); - regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK; - } while (regValue != 0x0U); - - if (mode == kNETC_XGMII10GAuto) - { - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, - ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE_MASK, - ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_INTR_STS, ®Value); - regValue &= ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_MASK; - } while (regValue == 0x0U); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_INTR_STS, ®Value); - regValue &= ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_USXG_AN_STS_MASK; - } while (regValue != ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_USXG_AN_STS(0x2FU)); - - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_INTR_STS, - ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_MASK, - ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR(0x0U)); - - NETC_PHYWriteRegBits(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST_MASK, - ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST(0x1U)); - do - { - NETC_PHYReadReg(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, ®Value); - regValue &= ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST_MASK; - } while (regValue != 0U); - } - } - else - { - return kStatus_NETC_Unsupported; - } -#endif - return kStatus_Success; + return NETC_MDIOC45Read(handle, portAddr, devAddr, regAddr, val); } diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_phy_wrapper.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_phy_wrapper.h index 422af77929..933378930f 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_phy_wrapper.h +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_phy_wrapper.h @@ -36,4 +36,27 @@ typedef enum _phy_mode */ status_t NETC_PHYInit(netc_mdio_handle_t *handle, phy_mode_t mode); +/*! + * @brief NETC PHY WRAPPER register bits write + * + * @param handle mdio handle. + * @param pcs pcs. + * @param reg register address. + * @param mask mask to write. + * @param val value to write. + * @return status_t + */ +status_t NETC_PHYWriteRegBits( + netc_mdio_handle_t *handle, bool pcs, volatile uint16_t *reg, uint16_t mask, uint16_t val); + +/*! + * @brief NETC PHY WRAPPER register read + * + * @param handle mdio handle. + * @param pcs pcs. + * @param reg register address. + * @param val read value. + * @return status_t + */ +status_t NETC_PHYReadReg(netc_mdio_handle_t *handle, bool pcs, const volatile uint16_t *reg, uint16_t *val); #endif /* _FSL_NETC_PHY_WRAPPER_H_ */ diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.c b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.c index df7a805007..02a524b7fd 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.c +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.c @@ -1,5 +1,5 @@ /* - * Copyright 2022-2024 NXP + * Copyright 2022-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,10 +11,14 @@ #include #endif +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.netc_switch" +#endif + /*! @name NETC register map. */ /*@{*/ -#define NETC_SWT_PORT_GROUP_BASE_OFFSET (0x4000U) /*!< The Switch port group register base address offset. */ -#define NETC_SWT_GLOBAL_BASE_OFFSET (0x80000U) /*!< The Switch global register base address offset. */ +#define NETC_SWT_PORT_GROUP_BASE_OFFSET (0x4000U) /*!< The Switch port group register base address offset. */ /*! @brief Pointers to netc bases for each instance. */ static ENETC_PCI_TYPE0_Type *const s_netcPciBases[] = ENETC_PCI_TYPE0_BASE_PTRS; @@ -34,7 +38,7 @@ static void SWT_GetBaseResource(swt_handle_t *handle, netc_hw_switch_idx_t sw) { handle->hw.func = s_netcPciBases[NETC_SOC_SWT_PCIE_FUNC_OFFSET + (uint32_t)sw]; handle->hw.base = s_netcSWBases[sw]; - handle->hw.common = (NETC_SW_ENETC_Type *)((uintptr_t)handle->hw.base); + handle->hw.common = (NETC_SW_ENETC_Type *)((uintptr_t)handle->hw.base + NETC_SWT_COMMON_BASE_OFFSET); handle->hw.global = (ENETC_GLOBAL_Type *)((uintptr_t)handle->hw.base + NETC_SWT_GLOBAL_BASE_OFFSET); for (uint32_t i = 0U; i < (uint32_t)FSL_FEATURE_NETC_SWITCH_MAX_PORT_NUMBER; i++) { @@ -42,8 +46,9 @@ static void SWT_GetBaseResource(swt_handle_t *handle, netc_hw_switch_idx_t sw) (NETC_PORT_Type *)((uintptr_t)handle->hw.base + (i + 1U) * NETC_SWT_PORT_GROUP_BASE_OFFSET); handle->hw.ports[i].eth = (NETC_ETH_LINK_Type *)((uintptr_t)handle->hw.ports[i].port + 0x1000U); } - handle->hw.msixTable = (netc_msix_entry_t *)((uint32_t)FSL_FEATURE_NETC_MSIX_TABLE_BASE + - NETC_MSIX_TABLE_OFFSET * (NETC_SOC_SWT_PCIE_FUNC_OFFSET + (uint32_t)sw)); + handle->hw.msixTable = + (netc_msix_entry_t *)((uint32_t)FSL_FEATURE_NETC_MSIX_TABLE_BASE + + NETC_MSIX_TABLE_OFFSET * (NETC_SOC_SWT_MSI_FUNC_OFFSET + (uint32_t)sw)); } /*! @@ -198,23 +203,24 @@ status_t SWT_GetDefaultConfig(swt_config_t *config) #if (defined(FSL_FEATURE_NETC_HAS_PORT_FCSEA) && FSL_FEATURE_NETC_HAS_PORT_FCSEA) config->ports[i].commonCfg.stompFcs = true; #endif - config->ports[i].commonCfg.rxPpduBco = 20U; - config->ports[i].commonCfg.txPpduBco = 20U; - config->ports[i].commonCfg.timeGate.holdSkew = 64; - config->ports[i].commonCfg.parser.l2PloadCount = 24; - config->ports[i].commonCfg.parser.l3PayloadCount = 24; - config->ports[i].commonCfg.parser.enableL3Parser = true; - config->ports[i].commonCfg.parser.l4PayloadCount = 24; - config->ports[i].commonCfg.parser.enableL4Parser = true; - config->ports[i].ethMac.preemptMode = kNETC_PreemptDisable; - config->ports[i].ethMac.enMergeVerify = false; - config->ports[i].ethMac.mergeVerifyTime = 10U; - config->ports[i].ethMac.enTxPad = true; - config->ports[i].ethMac.rxMinFrameSize = 64U; - config->ports[i].ethMac.rxMaxFrameSize = 0x600U; - config->ports[i].ethMac.maxBackPressOn = 3036U; - config->ports[i].ethMac.minBackPressOff = 20U; - config->ports[i].enTxRx = true; + config->ports[i].commonCfg.rxPpduBco = 20U; + config->ports[i].commonCfg.txPpduBco = 20U; + config->ports[i].commonCfg.timeGate.holdSkew = 64; + config->ports[i].commonCfg.parser.l2PloadCount = 24; + config->ports[i].commonCfg.parser.l3PayloadCount = 24; + config->ports[i].commonCfg.parser.enableL3Parser = true; + config->ports[i].commonCfg.parser.l4PayloadCount = 24; + config->ports[i].commonCfg.parser.enableL4Parser = true; + config->ports[i].ethMac.PreemptionConfig.preemptMode = kNETC_PreemptDisable; + config->ports[i].ethMac.PreemptionConfig.enMergeVerify = false; + config->ports[i].ethMac.PreemptionConfig.mergeVerifyTime = 10U; + config->ports[i].ethMac.PreemptionConfig.raf_size = kNETC_RafSize64; + config->ports[i].ethMac.enTxPad = true; + config->ports[i].ethMac.rxMinFrameSize = 64U; + config->ports[i].ethMac.rxMaxFrameSize = 0x600U; + config->ports[i].ethMac.maxBackPressOn = 3036U; + config->ports[i].ethMac.minBackPressOff = 20U; + config->ports[i].enTxRx = true; for (uint32_t j = 0U; j < 8U; j++) { config->ports[i].txTcCfg[j].enTcGate = true; @@ -365,18 +371,11 @@ status_t SWT_Init(swt_handle_t *handle, const swt_config_t *config) (void)SWT_FMConfigPort(handle, (netc_hw_port_idx_t)i, &config->ports[i].fmCfg); (void)NETC_PortSetISI(port, &config->ports[i].isiCfg); (void)NETC_PortConfig(port, &config->ports[i].commonCfg); - port->PMCR = NETC_PORT_PMCR_IMIRE(config->ports[i].enMirror); + port->PMCR = NETC_PORT_PMCR_IMIRE(config->ports[i].enMirror); #if defined(NETC_PORT_PLANIDCR_LANID) - port->PLANIDCR = NETC_PORT_PLANIDCR_LANID(config->ports[i].lanID); + port->PLANIDCR = NETC_PORT_PLANIDCR_LANID(config->ports[i].lanID); #endif - port->PIPV2QMR0 = NETC_PORT_PIPV2QMR0_IPV7_Q(config->ports[i].ipvToTC[7]) | - NETC_PORT_PIPV2QMR0_IPV6_Q(config->ports[i].ipvToTC[6]) | - NETC_PORT_PIPV2QMR0_IPV5_Q(config->ports[i].ipvToTC[5]) | - NETC_PORT_PIPV2QMR0_IPV4_Q(config->ports[i].ipvToTC[4]) | - NETC_PORT_PIPV2QMR0_IPV3_Q(config->ports[i].ipvToTC[3]) | - NETC_PORT_PIPV2QMR0_IPV2_Q(config->ports[i].ipvToTC[2]) | - NETC_PORT_PIPV2QMR0_IPV1_Q(config->ports[i].ipvToTC[1]) | - NETC_PORT_PIPV2QMR0_IPV0_Q(config->ports[i].ipvToTC[0]); + (void)SWT_SetPortIPV2QMR(handle, (netc_hw_port_idx_t)i, config->ports[i].ipvToTC); port->PBPMCR0 = NETC_PORT_PBPMCR0_IPV3_INDEX(config->ports[i].ipvToBP[3]) | NETC_PORT_PBPMCR0_IPV2_INDEX(config->ports[i].ipvToBP[2]) | NETC_PORT_PBPMCR0_IPV1_INDEX(config->ports[i].ipvToBP[1]) | @@ -593,9 +592,11 @@ static void SWT_StoreTransConfig(swt_handle_t *handle, const swt_transfer_config handle->cfg.rxBuffAlloc = config->rxBuffAlloc; handle->cfg.rxBuffFree = config->rxBuffFree; handle->cfg.enUseMgmtRxBdRing = config->enUseMgmtRxBdRing; +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) handle->cfg.enUseMgmtTxBdRing = config->enUseMgmtTxBdRing; - handle->cfg.reclaimCallback = config->reclaimCallback; - handle->cfg.userData = config->userData; +#endif + handle->cfg.reclaimCallback = config->reclaimCallback; + handle->cfg.userData = config->userData; } status_t SWT_ManagementTxRxConfig(swt_handle_t *handle, ep_handle_t *epHandle, const swt_transfer_config_t *txRxConfig) @@ -685,6 +686,7 @@ status_t SWT_ManagementTxRxConfig(swt_handle_t *handle, ep_handle_t *epHandle, c /* Enable the Rx BD ring. */ NETC_SIRxRingEnable(epHandle->hw.si, mgmtRxBdRingIdx, true); } + if (txRxConfig->enUseMgmtTxBdRing) { /* Management Tx ring only can be SI 0 ring 0 */ @@ -696,11 +698,67 @@ status_t SWT_ManagementTxRxConfig(swt_handle_t *handle, ep_handle_t *epHandle, c handle->mgmtTxBdRing.dirtyBase = txRxConfig->mgmtTxBdrConfig.dirtyArray; handle->mgmtTxBdRing.len = txRxConfig->mgmtTxBdrConfig.len; } + return kStatus_Success; } +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG +status_t SWT_SendFrame(swt_handle_t *handle, netc_frame_struct_t *frame, void *context, swt_tx_opt *opt) +{ + netc_tx_bdr_t *txBdRing = &handle->mgmtTxBdRing; + netc_tx_bd_t txDesc[2] = {0}; + + if (opt != NULL) + { + if ((opt->flags & (uint32_t)kSWT_TX_OPT_VLAN_INSERT) != 0U) + { + txDesc[0].standard.isExtended = 1U; + txDesc[1].ext.pcp = opt->vlan.pcp; + txDesc[1].ext.dei = opt->vlan.dei; + txDesc[1].ext.vid = opt->vlan.vid; + txDesc[1].ext.tpid = (uint16_t)opt->vlan.tpid; + txDesc[1].ext.eFlags = (uint8_t)kNETC_TxExtVlanInsert; + } + + if ((opt->flags & (uint32_t)kSWT_TX_OPT_OFFLOAD) != 0U) + { + txDesc[0].standard.flags = NETC_SI_TXDESCRIP_RD_FL(1) | NETC_SI_TXDESCRIP_RD_LSO(opt->offload.lso) | + NETC_SI_TXDESCRIP_RD_L4CS(opt->offload.l4Checksum) | + NETC_SI_TXDESCRIP_RD_L4T(opt->offload.l4Type) | + NETC_SI_TXDESCRIP_RD_L3T(opt->offload.l3Type) | + NETC_SI_TXDESCRIP_RD_L3HDRSIZE(opt->offload.l3HeaderSize) | + NETC_SI_TXDESCRIP_RD_IPCS(opt->offload.ipv4Checksum) | + NETC_SI_TXDESCRIP_RD_L3START(opt->offload.l3Start); + + txDesc[0].standard.isExtended = (opt->offload.lso) ? 1U : 0U; + txDesc[1].ext.lsoMaxSegSize = opt->offload.lsoMaxSegSize; + } + } + + return EP_SendFrameCommon(handle->epHandle, txBdRing, opt == NULL ? 0U : opt->ring, frame, context, &txDesc[0], + handle->cfg.txCacheMaintain); +} + +void SWT_ReclaimTxDescriptor(swt_handle_t *handle, uint8_t ring) +{ + netc_tx_frame_info_t *frameInfo; + + do + { + frameInfo = + EP_ReclaimTxDescCommon(handle->epHandle, &handle->mgmtTxBdRing, 0, (handle->cfg.reclaimCallback != NULL)); + if (frameInfo != NULL) + { + /* If reclaim callback is enabled, it must be called for each full frame. */ + (void)handle->cfg.reclaimCallback(handle, frameInfo, handle->cfg.userData); + (void)memset(frameInfo, 0, sizeof(netc_tx_frame_info_t)); + } + } while (frameInfo != NULL); +} + +#else status_t SWT_SendFrame(swt_handle_t *handle, - swt_mgmt_tx_arg_t ringOrQueue, + swt_mgmt_tx_arg_t txArg, netc_hw_port_idx_t swtPort, bool enMasquerade, netc_frame_struct_t *frame, @@ -716,14 +774,14 @@ status_t SWT_SendFrame(swt_handle_t *handle, { /* Switch management ENETC Tx BD hardware ring 0 can't be used to send port masqueradeque frame, so the * index need increase 1 */ - hwRing = ringOrQueue.ring + 1U; + hwRing = txArg.ring + 1U; } else { - hwRing = ringOrQueue.ring; + hwRing = txArg.ring; } txDesc[0].standard.flags = NETC_SI_TXDESCRIP_RD_FLQ(2) | NETC_SI_TXDESCRIP_RD_PORT(swtPort); - txBdRing = &handle->epHandle->txBdRing[ringOrQueue.ring]; + txBdRing = &handle->epHandle->txBdRing[txArg.ring]; } else { @@ -733,8 +791,8 @@ status_t SWT_SendFrame(swt_handle_t *handle, return kStatus_InvalidArgument; } txDesc[0].standard.flags = NETC_SI_TXDESCRIP_RD_FLQ(2) | NETC_SI_TXDESCRIP_RD_SMSO_MASK | - NETC_SI_TXDESCRIP_RD_PORT(swtPort) | NETC_SI_TXDESCRIP_RD_IPV(ringOrQueue.ipv) | - NETC_SI_TXDESCRIP_RD_DR(ringOrQueue.dr); + NETC_SI_TXDESCRIP_RD_PORT(swtPort) | NETC_SI_TXDESCRIP_RD_IPV(txArg.ipv) | + NETC_SI_TXDESCRIP_RD_DR(txArg.dr); hwRing = 0U; txBdRing = &handle->mgmtTxBdRing; } @@ -805,36 +863,6 @@ void SWT_ReclaimTxDescriptor(swt_handle_t *handle, bool enMasquerade, uint8_t ri } while (frameInfo != NULL); } -status_t SWT_GetRxFrameSize(swt_handle_t *handle, uint32_t *length) -{ - assert((handle != NULL) && (length != NULL)); - netc_rx_bdr_t *rxBdRing = NULL; - status_t result; - - if (handle->cfg.enUseMgmtRxBdRing) - { - rxBdRing = &handle->mgmtRxBdRing; - } - else if (handle->epHandle->cfg.rxRingUse != 0U) - { - /* If no management Rx ring is specified, the host reason not zero frames will be received by Rx ring 0 */ - rxBdRing = &handle->epHandle->rxBdRing[0]; - } - else - { - /* If both the switch and its associated EP not config the Rx BD ring, no frame can be received */ - return kStatus_InvalidArgument; - } - - result = EP_GetRxFrameSizeCommon(handle->epHandle, rxBdRing, length); - if (kStatus_NETC_RxHRNotZeroFrame == result) - { - /* Only return success when currently frame is host reason not zero frame */ - result = kStatus_Success; - } - return result; -} - status_t SWT_GetTimestampRefResp(swt_handle_t *handle, swt_tsr_resp_t *tsr) { status_t result = kStatus_Fail; @@ -892,6 +920,37 @@ status_t SWT_GetTimestampRefResp(swt_handle_t *handle, swt_tsr_resp_t *tsr) return result; } +#endif + +status_t SWT_GetRxFrameSize(swt_handle_t *handle, uint32_t *length) +{ + assert((handle != NULL) && (length != NULL)); + netc_rx_bdr_t *rxBdRing = NULL; + status_t result; + + if (handle->cfg.enUseMgmtRxBdRing) + { + rxBdRing = &handle->mgmtRxBdRing; + } + else if (handle->epHandle->cfg.rxRingUse != 0U) + { + /* If no management Rx ring is specified, the host reason not zero frames will be received by Rx ring 0 */ + rxBdRing = &handle->epHandle->rxBdRing[0]; + } + else + { + /* If both the switch and its associated EP not config the Rx BD ring, no frame can be received */ + return kStatus_InvalidArgument; + } + + result = EP_GetRxFrameSizeCommon(handle->epHandle, rxBdRing, length); + if (kStatus_NETC_RxHRNotZeroFrame == result) + { + /* Only return success when currently frame is host reason not zero frame */ + result = kStatus_Success; + } + return result; +} status_t SWT_ReceiveFrameCopy(swt_handle_t *handle, void *buffer, uint32_t length, netc_frame_attr_t *attr) { @@ -1159,16 +1218,16 @@ status_t SWT_BridgeInit(swt_handle_t *handle, const netc_swt_bridge_config_t *co assert(config != NULL); /* Configure switch default VLAN filter entry */ - handle->hw.base->VFHTDECR0 = - NETC_SW_VFHTDECR0_IPMFLE(config->dVFCfg.enIPMFlood) | NETC_SW_VFHTDECR0_IPMFE(config->dVFCfg.enIPMFilter) | - NETC_SW_VFHTDECR0_STG_ID(config->dVFCfg.stgID) | - ((config->dVFCfg.portMembership << NETC_SW_VFHTDECR0_PORT0_SHIFT) & - ( + handle->hw.base->VFHTDECR0 = NETC_SW_VFHTDECR0_IPMFLE(config->dVFCfg.enIPMFlood) | + NETC_SW_VFHTDECR0_IPMFE(config->dVFCfg.enIPMFilter) | + NETC_SW_VFHTDECR0_STG_ID(config->dVFCfg.stgID) | + ((config->dVFCfg.portMembership << NETC_SW_VFHTDECR0_PORT0_SHIFT) & + ( #if defined(NETC_SW_VFHTDECR0_PORT4_MASK) - NETC_SW_VFHTDECR0_PORT4_MASK | + NETC_SW_VFHTDECR0_PORT4_MASK | #endif - NETC_SW_VFHTDECR0_PORT3_MASK | NETC_SW_VFHTDECR0_PORT2_MASK | - NETC_SW_VFHTDECR0_PORT1_MASK | NETC_SW_VFHTDECR0_PORT0_MASK)); + NETC_SW_VFHTDECR0_PORT3_MASK | NETC_SW_VFHTDECR0_PORT2_MASK | + NETC_SW_VFHTDECR0_PORT1_MASK | NETC_SW_VFHTDECR0_PORT0_MASK)); #if defined(NETC_SW_VFHTDECR1_ET_EID) handle->hw.base->VFHTDECR1 = NETC_SW_VFHTDECR1_ET_EID(config->dVFCfg.baseETEID) | #else @@ -1176,38 +1235,37 @@ status_t SWT_BridgeInit(swt_handle_t *handle, const netc_swt_bridge_config_t *co #endif NETC_SW_VFHTDECR1_VL_MODE(config->dVFCfg.enUseFilterID) | NETC_SW_VFHTDECR1_FID(config->dVFCfg.filterID); - handle->hw.base->VFHTDECR2 = - NETC_SW_VFHTDECR2_MFO(config->dVFCfg.mfo) | NETC_SW_VFHTDECR2_MLO(config->dVFCfg.mlo) | + handle->hw.base->VFHTDECR2 = NETC_SW_VFHTDECR2_MFO(config->dVFCfg.mfo) | NETC_SW_VFHTDECR2_MLO(config->dVFCfg.mlo) | #if defined(NETC_SW_VFHTDECR2_ETA_PORT0_SHIFT) - ((config->dVFCfg.etaPortBitmap << NETC_SW_VFHTDECR2_ETA_PORT0_SHIFT) & + ((config->dVFCfg.etaPortBitmap << NETC_SW_VFHTDECR2_ETA_PORT0_SHIFT) & #else - ((config->dVFCfg.etaPortBitmap << NETC_SW_VFHTDECR2_ET_PORT0_SHIFT) & + ((config->dVFCfg.etaPortBitmap << NETC_SW_VFHTDECR2_ET_PORT0_SHIFT) & #endif - ( + ( #if defined(NETC_SW_VFHTDECR2_ET_PORT4_MASK) - NETC_SW_VFHTDECR2_ET_PORT4_MASK | + NETC_SW_VFHTDECR2_ET_PORT4_MASK | #endif #if defined(NETC_SW_VFHTDECR2_ETA_PORT3_MASK) - NETC_SW_VFHTDECR2_ETA_PORT3_MASK | + NETC_SW_VFHTDECR2_ETA_PORT3_MASK | #else - NETC_SW_VFHTDECR2_ET_PORT3_MASK | + NETC_SW_VFHTDECR2_ET_PORT3_MASK | #endif #if defined(NETC_SW_VFHTDECR2_ETA_PORT2_MASK) - NETC_SW_VFHTDECR2_ETA_PORT2_MASK | + NETC_SW_VFHTDECR2_ETA_PORT2_MASK | #else - NETC_SW_VFHTDECR2_ET_PORT2_MASK | + NETC_SW_VFHTDECR2_ET_PORT2_MASK | #endif #if defined(NETC_SW_VFHTDECR2_ETA_PORT1_MASK) - NETC_SW_VFHTDECR2_ETA_PORT1_MASK | + NETC_SW_VFHTDECR2_ETA_PORT1_MASK | #else - NETC_SW_VFHTDECR2_ET_PORT1_MASK | + NETC_SW_VFHTDECR2_ET_PORT1_MASK | #endif #if defined(NETC_SW_VFHTDECR2_ETA_PORT0_MASK) - NETC_SW_VFHTDECR2_ETA_PORT0_MASK + NETC_SW_VFHTDECR2_ETA_PORT0_MASK #else - NETC_SW_VFHTDECR2_ET_PORT0_MASK + NETC_SW_VFHTDECR2_ET_PORT0_MASK #endif - )); + )); return kStatus_Success; } @@ -1242,11 +1300,10 @@ status_t SWT_BridgeConfigPort(swt_handle_t *handle, return kStatus_Success; } -status_t SWT_BridgeConfigPortDefaultVid(swt_handle_t *handle, - netc_hw_port_idx_t portIdx, uint16_t vid) +status_t SWT_BridgeConfigPortDefaultVid(swt_handle_t *handle, netc_hw_port_idx_t portIdx, uint16_t vid) { assert(handle != NULL); - NETC_PORT_Type *base = handle->hw.ports[portIdx].port; + NETC_PORT_Type *base = handle->hw.ports[portIdx].port; base->BPDVR = (base->BPDVR & ~NETC_PORT_BPDVR_VID_MASK) | NETC_PORT_BPDVR_VID(vid); @@ -1314,8 +1371,8 @@ status_t SWT_BridgeUpdateVFTableEntry(swt_handle_t *handle, uint32_t entryID, ne } status_t SWT_BridgeSearchVFTableEntry(swt_handle_t *handle, - netc_tb_vf_search_criteria_t *sCriteria, - netc_tb_vf_rsp_data_t *rsp) + netc_tb_vf_search_criteria_t *sCriteria, + netc_tb_vf_rsp_data_t *rsp) { assert((handle != NULL) && (sCriteria != NULL) && (rsp != NULL)); netc_cmd_bd_t cmdBd = {0}; @@ -1328,12 +1385,12 @@ status_t SWT_BridgeSearchVFTableEntry(swt_handle_t *handle, /* Query entry in VF Table based on the search criteria */ cdbrHandle.buffer->vf.request.sCriteria = *sCriteria; cdbrHandle.buffer->vf.request.commonHeader.queryActions = 0U; - cmdBd.req.addr = (uintptr_t)cdbrHandle.buffer; - cmdBd.req.reqLength = sizeof(netc_tb_vf_req_data_t); - cmdBd.req.resLength = sizeof(netc_tb_vf_rsp_data_t); - cmdBd.req.tableId = kNETC_VFTable; - cmdBd.req.cmd = kNETC_QueryEntry; - cmdBd.req.accessType = kNETC_Search; + cmdBd.req.addr = (uintptr_t)cdbrHandle.buffer; + cmdBd.req.reqLength = sizeof(netc_tb_vf_req_data_t); + cmdBd.req.resLength = sizeof(netc_tb_vf_rsp_data_t); + cmdBd.req.tableId = kNETC_VFTable; + cmdBd.req.cmd = kNETC_QueryEntry; + cmdBd.req.accessType = kNETC_Search; status = NETC_CmdBDSendCommand(cdbrHandle.base, cdbrHandle.cmdr, &cmdBd, kNETC_NtmpV2_0); if (kStatus_Success == status) { @@ -1351,9 +1408,7 @@ status_t SWT_BridgeSearchVFTableEntry(swt_handle_t *handle, return status; } -status_t SWT_BridgeQueryVFTableEntry(swt_handle_t *handle, - netc_tb_vf_keye_t *keye, - netc_tb_vf_rsp_data_t *rsp) +status_t SWT_BridgeQueryVFTableEntry(swt_handle_t *handle, netc_tb_vf_keye_t *keye, netc_tb_vf_rsp_data_t *rsp) { assert((handle != NULL) && (keye != NULL) && (rsp != NULL)); netc_cmd_bd_t cmdBd = {0}; @@ -1364,14 +1419,14 @@ status_t SWT_BridgeQueryVFTableEntry(swt_handle_t *handle, { (void)memset(cdbrHandle.buffer, 0, sizeof(netc_tb_fdb_req_data_t)); /* Query entry in VF Table based on the exact match criteria */ - cdbrHandle.buffer->vf.request.keye = *keye; + cdbrHandle.buffer->vf.request.keye = *keye; cdbrHandle.buffer->vf.request.commonHeader.queryActions = 0U; - cmdBd.req.addr = (uintptr_t)cdbrHandle.buffer; - cmdBd.req.reqLength = sizeof(netc_tb_vf_req_data_t); - cmdBd.req.resLength = sizeof(netc_tb_vf_rsp_data_t); - cmdBd.req.tableId = kNETC_VFTable; - cmdBd.req.cmd = kNETC_QueryEntry; - cmdBd.req.accessType = kNETC_ExactKeyMatch; + cmdBd.req.addr = (uintptr_t)cdbrHandle.buffer; + cmdBd.req.reqLength = sizeof(netc_tb_vf_req_data_t); + cmdBd.req.resLength = sizeof(netc_tb_vf_rsp_data_t); + cmdBd.req.tableId = kNETC_VFTable; + cmdBd.req.cmd = kNETC_QueryEntry; + cmdBd.req.accessType = kNETC_ExactKeyMatch; status = NETC_CmdBDSendCommand(cdbrHandle.base, cdbrHandle.cmdr, &cmdBd, kNETC_NtmpV2_0); if (kStatus_Success == status) { @@ -1389,7 +1444,6 @@ status_t SWT_BridgeQueryVFTableEntry(swt_handle_t *handle, return status; } - status_t SWT_BridgeDelVFTableEntry(swt_handle_t *handle, uint32_t entryID) { assert(handle != NULL); @@ -1514,9 +1568,7 @@ status_t SWT_BridgeSearchFDBTableEntry(swt_handle_t *handle, return status; } -status_t SWT_BridgeQueryFDBTableEntry(swt_handle_t *handle, - netc_tb_fdb_keye_t *keye, - netc_tb_fdb_rsp_data_t *rsp) +status_t SWT_BridgeQueryFDBTableEntry(swt_handle_t *handle, netc_tb_fdb_keye_t *keye, netc_tb_fdb_rsp_data_t *rsp) { assert((handle != NULL) && (keye != NULL) && (rsp != NULL)); netc_cmd_bd_t cmdBd = {0}; @@ -1527,7 +1579,7 @@ status_t SWT_BridgeQueryFDBTableEntry(swt_handle_t *handle, { (void)memset(cdbrHandle.buffer, 0, sizeof(netc_tb_fdb_req_data_t)); /* Query entry in FDB Table based on the exact match criteria */ - cdbrHandle.buffer->fdb.request.keye = *keye; + cdbrHandle.buffer->fdb.request.keye = *keye; cdbrHandle.buffer->fdb.request.commonHeader.queryActions = 0U; cmdBd.req.addr = (uintptr_t)cdbrHandle.buffer; cmdBd.req.reqLength = sizeof(netc_tb_fdb_req_data_t); @@ -1788,7 +1840,9 @@ status_t SWT_RxPSFPQueryISITableEntry(swt_handle_t *handle, uint32_t entryID, ne } } -status_t SWT_RxPSFPQueryISITableEntryWithKey(swt_handle_t *handle, netc_tb_isi_keye_t *keye, netc_tb_isi_rsp_data_t *rsp) +status_t SWT_RxPSFPQueryISITableEntryWithKey(swt_handle_t *handle, + netc_tb_isi_keye_t *keye, + netc_tb_isi_rsp_data_t *rsp) { assert((handle != NULL) && (keye != NULL) && (rsp != NULL)); netc_cbdr_handle_t cdbrHandle; @@ -2012,6 +2066,20 @@ status_t SWT_RxPSFPUpdateSGITableEntry(swt_handle_t *handle, netc_tb_sgi_config_ return kStatus_NETC_LackOfResource; } } +status_t SWT_RxPSFPResetIRXOEXSGITableEntry(swt_handle_t *handle, uint32_t entryID) +{ + assert(handle != NULL); + netc_cbdr_handle_t cdbrHandle; + + if (SWT_GetIdleCmdBDRing(handle, &cdbrHandle) == kStatus_Success) + { + return NETC_ResetIRXOEXSGITableEntry(&cdbrHandle, entryID); + } + else + { + return kStatus_NETC_LackOfResource; + } +} status_t SWT_RxPSFPDelSGITableEntry(swt_handle_t *handle, uint32_t entryID) { @@ -2030,7 +2098,7 @@ status_t SWT_RxPSFPDelSGITableEntry(swt_handle_t *handle, uint32_t entryID) status_t SWT_RxPSFPGetSGIState(swt_handle_t *handle, uint32_t entryID, netc_tb_sgi_sgise_t *state) { - assert(handle != NULL); + assert((handle != NULL) && (state != NULL)); netc_cbdr_handle_t cdbrHandle; if (SWT_GetIdleCmdBDRing(handle, &cdbrHandle) == kStatus_Success) @@ -2043,14 +2111,14 @@ status_t SWT_RxPSFPGetSGIState(swt_handle_t *handle, uint32_t entryID, netc_tb_s } } -status_t SWT_RxPSFPQuerySGITableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_sgi_rsp_data_t *rsp) +status_t SWT_RxPSFPQuerySGITableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_sgi_config_t *config) { - assert((handle != NULL) && (rsp != NULL)); + assert((handle != NULL) && (config != NULL)); netc_cbdr_handle_t cdbrHandle; if (SWT_GetIdleCmdBDRing(handle, &cdbrHandle) == kStatus_Success) { - return NETC_QuerySGITableEntry(&cdbrHandle, entryID, rsp); + return NETC_QuerySGITableEntry(&cdbrHandle, entryID, config); } else { @@ -2170,7 +2238,7 @@ status_t SWT_RxPSFPResetMRRPTableEntry(swt_handle_t *handle, uint32_t entryID) if (SWT_GetIdleCmdBDRing(handle, &cdbrHandle) == kStatus_Success) { - return NETC_ResetMRRPTableEntry(&cdbrHandle, entryID); + return NETC_ResetMRRPTableEntry(&cdbrHandle, entryID); } else { @@ -2235,8 +2303,7 @@ status_t SWT_TxTrafficClassConfig(swt_handle_t *handle, if (!NETC_PortIsPseudo(base)) { - temp = base->PFPCR & (~((uint32_t)1U << (uint8_t)tcIdx)); - base->PFPCR = temp | ((uint32_t)config->enPreemption << (uint8_t)tcIdx); + NETC_PortConfigTcPreemption(base, tcIdx, config->enPreemption); } temp = base->PDGSR & (~((uint32_t)1U << (uint32_t)tcIdx)); base->PDGSR = temp | ((uint32_t)config->enTcGate << (uint32_t)tcIdx); @@ -2265,7 +2332,7 @@ status_t SWT_TxPortTGSEnable(swt_handle_t *handle, netc_hw_port_idx_t portIdx, b netc_tgs_gate_entry_t gate[2] = {{.interval = 50000U, .tcGateState = gateState}, {.interval = 50000U, .tcGateState = gateState}}; netc_tb_tgs_gcl_t wTgsList = { - .entryID = (netc_tb_tgs_entry_id_t)portIdx, .cycleTime = 1000000U, .numEntries = 2U, .gcList = &gate[0]}; + .entryID = (netc_tb_tgs_entry_id_t)portIdx, .cycleTime = 1000000U, .numEntries = 2U, .gcList = &gate[0]}; uint64_t time; /* Enable master bus and memory access for default ns timer*/ TMR_PCI_HDR_TYPE0->PCI_CFH_CMD |= @@ -2310,7 +2377,7 @@ status_t SWT_TxTGSConfigAdminGcl(swt_handle_t *handle, netc_tb_tgs_gcl_t *config uint64_t time, minBaseTime; /* Read the previous active Operationa gate control list cycle time*/ - (void)memset(cdbrHandle.buffer, 0, sizeof(netc_tb_tgs_data_t)); + (void)memset(cdbrHandle.buffer, 0, sizeof(netc_tb_tgs_req_data_t)); cdbrHandle.buffer->tgs.request.entryID = config->entryID; cdbrHandle.buffer->tgs.request.commonHeader.updateActions = 0U; cdbrHandle.buffer->tgs.request.commonHeader.queryActions = 0U; @@ -2448,6 +2515,35 @@ status_t SWT_FMDelTableEntry(swt_handle_t *handle, uint32_t entryID) } } +status_t SWT_FMQueryTableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_fm_config_t *config) +{ + netc_cmd_bd_t cmdBd = {0}; + netc_cbdr_handle_t cdbrHandle; + status_t status = kStatus_NETC_LackOfResource; + + if (SWT_GetIdleCmdBDRing(handle, &cdbrHandle) == kStatus_Success) + { + (void)memset(cdbrHandle.buffer, 0, sizeof(netc_tb_fm_config_t)); + cdbrHandle.buffer->fm.request.entryID = entryID; + cdbrHandle.buffer->fm.request.commonHeader.updateActions = 0U; + cdbrHandle.buffer->fm.request.commonHeader.queryActions = 0U; + cmdBd.req.addr = (uintptr_t)cdbrHandle.buffer; + cmdBd.req.reqLength = 8U; + cmdBd.req.resLength = sizeof(netc_tb_fm_config_t); + cmdBd.req.tableId = kNETC_FMTable; + cmdBd.req.cmd = kNETC_QueryEntry; + /* Only support Entry ID Match */ + cmdBd.req.accessType = kNETC_EntryIDMatch; + status = NETC_CmdBDSendCommand(cdbrHandle.base, cdbrHandle.cmdr, &cmdBd, kNETC_NtmpV2_0); + if (kStatus_Success == status) + { + (void)memcpy(&config->cfge, &cdbrHandle.buffer->fm.response.cfge, sizeof(netc_tb_fm_cfge_t)); + } + } + + return status; +} + status_t SWT_FMDUpdateTableEntry(swt_handle_t *handle, netc_tb_fmd_update_config_t *config, uint32_t length) { netc_cmd_bd_t cmdBd = {0}; @@ -2584,7 +2680,7 @@ status_t SWT_TxEPPQueryETTableEntry(swt_handle_t *handle, uint32_t entryID, netc if (0U != cmdBd.resp.numMatched) { config->entryID = cdbrHandle.buffer->et.response.entryID; - config->cfge = cdbrHandle.buffer->et.response.cfge; + config->cfge = cdbrHandle.buffer->et.response.cfge; } else { @@ -3025,10 +3121,10 @@ status_t SWT_FRERConfigESEQRTableEntry(swt_handle_t *handle, netc_tb_eseqr_confi } status_t SWT_FRERQueryESEQRTableEntry(swt_handle_t *handle, - uint32_t entryID, - netc_tb_eseqr_stse_t *statistic, - netc_tb_eseqr_cfge_t *config, - netc_tb_eseqr_srse_t *state) + uint32_t entryID, + netc_tb_eseqr_stse_t *statistic, + netc_tb_eseqr_cfge_t *config, + netc_tb_eseqr_srse_t *state) { assert(handle != NULL); @@ -3060,10 +3156,10 @@ status_t SWT_FRERQueryESEQRTableEntry(swt_handle_t *handle, if (config != NULL) { - *config = cdbrHandle.buffer->eseqr.response.cfge; + *config = cdbrHandle.buffer->eseqr.response.cfge; } - *state = cdbrHandle.buffer->eseqr.response.srse; + *state = cdbrHandle.buffer->eseqr.response.srse; } } diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.h index f87b4fe602..52698e12a6 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.h +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_switch.h @@ -1,5 +1,5 @@ /* - * Copyright 2021-2024 NXP + * Copyright 2021-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,11 +9,17 @@ #include "fsl_netc.h" #include "fsl_netc_endpoint.h" +#include "fsl_netc_tag.h" #include "netc_hw/fsl_netc_hw.h" #include "netc_hw/fsl_netc_hw_enetc.h" #include "netc_hw/fsl_netc_hw_port.h" #include "netc_hw/fsl_netc_hw_si.h" +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG +#ifndef NETC_SWITCH_ID +#define NETC_SWITCH_ID (1U) +#endif +#endif #if !(defined(__GNUC__) || defined(__ICCARM__)) #pragma region api_swt #endif @@ -189,7 +195,9 @@ typedef struct _swt_config_const bool rxCacheMaintain : 1; /*!< Enable/Disable Rx buffer cache maintain in driver. */ bool txCacheMaintain : 1; /*!< Enable/Disable Tx buffer cache maintain in driver. */ bool enUseMgmtRxBdRing : 1; /*!< Enable/Disable use Switch management Rx BD ring. */ +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) bool enUseMgmtTxBdRing : 1; /*!< Enable/Disable use Switch management Tx BD ring. */ +#endif bool rxZeroCopy : 1; /*!< Enable zero-copy receive mode. */ swt_rx_alloc_cb_t rxBuffAlloc; /*!< Callback function to alloc memory, must be provided for zero-copy Rx. */ swt_rx_free_cb_t rxBuffFree; /*!< Callback function to free memory, must be provided for zero-copy Rx. */ @@ -231,16 +239,6 @@ struct _swt_handle /*! @addtogroup netc_swt_xfer * @{ */ -/*! @brief Switch management Tx Option flags */ -typedef enum _swt_mgmt_tx_opt_flags -{ - kSWT_TX_OPT_REQ_TS = - 0x1, /*!< Request frame transmission timestamp, only active when use Switch Port masquerading Tx option */ - kSWT_TX_OPT_VLAN_INSERT = 0x2U, /*!< Enable VLAN insert, only active when use Switch Port masquerading Tx option */ - kSWT_TX_OPT_DIRECT_ENQUEUE_REQ_TSR = - 0x4U /*!< Timestamp Reference Request, only active when use Direct Switch Enqueue Tx option */ -} swt_mgmt_tx_opt_flags; - /*! @brief Switch management Tx parameter */ typedef union _swt_mgmt_tx_arg_t { @@ -253,10 +251,38 @@ typedef union _swt_mgmt_tx_arg_t }; } swt_mgmt_tx_arg_t; +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG +/*! @brief Switch management Tx Option flags */ +typedef enum _swt_mgmt_tx_opt_flags +{ + kSWT_TX_OPT_VLAN_INSERT = 0x1U, /*!< Enable VLAN insert, only active when use Switch Port masquerading Tx option. */ + kSWT_TX_OPT_OFFLOAD = 0x2U /*!< Tx offload. */ +} swt_mgmt_tx_opt_flags; + +typedef struct _swt_tx_opt +{ + uint8_t ring; /*!< Tx ring index. */ + uint32_t flags; /*!< A bitmask of @swt_mgmt_tx_opt_flags. */ + netc_enetc_vlan_tag_t vlan; /*!< VLAN tag which will be inserted, used if enVlanInsert is set. */ + netc_tx_offload_t offload; /*!< Offload parameters. */ +} swt_tx_opt; + +#else + +/*! @brief Switch management Tx Option flags */ +typedef enum _swt_mgmt_tx_opt_flags +{ + kSWT_TX_OPT_REQ_TS = + 0x1, /*!< Request frame transmission timestamp, only active when use Switch Port masquerading Tx option */ + kSWT_TX_OPT_VLAN_INSERT = 0x2U, /*!< Enable VLAN insert, only active when use Switch Port masquerading Tx option */ + kSWT_TX_OPT_DIRECT_ENQUEUE_REQ_TSR = + 0x4U /*!< Timestamp Reference Request, only active when use Direct Switch Enqueue Tx option */ +} swt_mgmt_tx_opt_flags; + /*! @brief Switch management Tx Option */ typedef struct _swt_tx_opt { - uint32_t flags; /*!< A bitmask of swt_mgmt_tx_opt_flags */ + uint32_t flags; /*!< A bitmask of @swt_mgmt_tx_opt_flags */ netc_enetc_vlan_tag_t vlan; /*!< VLAN tag which will be inserted, used if enVlanInsert is set */ } swt_tx_opt; @@ -266,6 +292,7 @@ typedef struct _swt_tsr_resp_t uint32_t timestamp; /*!< Switch response timestamp. */ uint32_t txtsid; /*!< Transmit timestamp identifier. */ } swt_tsr_resp_t; +#endif /* FSL_FEATURE_NETC_HAS_SWITCH_TAG */ /*! * @brief Transfer configuration structure for Switch @@ -283,9 +310,9 @@ struct _swt_transfer_config bool enUseMgmtRxBdRing; /*!< Enable/Disable use Switch management Rx BD ring, if disabled, the Switch/EP receive APIs (SWT_GetRxFrameSize()/SWT_ReceiveFrameCopy()/SWT_GetTimestampRefResp()/SWT_ReceiveFrame()) will use EP Rx BD ring 0 to receive frames. */ + netc_rx_bdr_config_t mgmtRxBdrConfig; /*!< Switch management Rx BD ring configuration. */ bool enUseMgmtTxBdRing; /*!< Enable/Disable use Switch management Tx BD ring, if disabled, can't use Switch transfer API (SWT_SendFrame()) to send frames. */ - netc_rx_bdr_config_t mgmtRxBdrConfig; /*!< Switch management Rx BD ring configuration. */ netc_tx_bdr_config_t mgmtTxBdrConfig; /*!< Switch management Rx BD ring configuration. */ swt_reclaim_cb_t reclaimCallback; /*!< Callback for reclaimed Tx Switch management frames. */ void *userData; /*!< User data, return in callback. */ @@ -766,7 +793,9 @@ status_t SWT_RxPSFPQueryISITableEntry(swt_handle_t *handle, uint32_t entryID, ne * @param rsp * @return status_t */ -status_t SWT_RxPSFPQueryISITableEntryWithKey(swt_handle_t *handle, netc_tb_isi_keye_t *keye, netc_tb_isi_rsp_data_t *rsp); +status_t SWT_RxPSFPQueryISITableEntryWithKey(swt_handle_t *handle, + netc_tb_isi_keye_t *keye, + netc_tb_isi_rsp_data_t *rsp); /*! * @brief Delete an entry in the stream identification table @@ -1076,6 +1105,15 @@ static inline uint32_t SWT_RxPSFPGetSGITableMaxEntryNum(swt_handle_t *handle) */ status_t SWT_RxPSFPAddSGITableEntry(swt_handle_t *handle, netc_tb_sgi_config_t *config); +/*! + * @brief Reset IRX and OEX flag in stream gate instance entry + * + * @param handle + * @return status_t + * @return See @ref netc_cmd_error_t + */ +status_t SWT_RxPSFPResetIRXOEXSGITableEntry(swt_handle_t *handle, uint32_t entryID); + /*! * @brief Update entry in stream gate instance table * @@ -1112,10 +1150,10 @@ status_t SWT_RxPSFPGetSGIState(swt_handle_t *handle, uint32_t entryID, netc_tb_s * * @param handle * @param entryID - * @param rsp + * @param config * @return See @ref netc_cmd_error_t */ -status_t SWT_RxPSFPQuerySGITableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_sgi_rsp_data_t *rsp); +status_t SWT_RxPSFPQuerySGITableEntry(swt_handle_t *handle, uint32_t entryID, netc_tb_sgi_config_t *config); /*! * @brief Get remaining available words number of Stream Gate Control List table @@ -1240,8 +1278,7 @@ status_t SWT_BridgeConfigPort(swt_handle_t *handle, * @param vid * @return status_t */ -status_t SWT_BridgeConfigPortDefaultVid(swt_handle_t *handle, - netc_hw_port_idx_t portIdx, uint16_t vid); +status_t SWT_BridgeConfigPortDefaultVid(swt_handle_t *handle, netc_hw_port_idx_t portIdx, uint16_t vid); /*! * @brief Get remaining available entry number (entry size is 24 bytes) of bridge vlan filter table @@ -1311,7 +1348,9 @@ status_t SWT_BridgeDelVFTableEntry(swt_handle_t *handle, uint32_t entryID); * @return status_t * @return See @ref netc_cmd_error_t */ -status_t SWT_BridgeSearchVFTableEntry(swt_handle_t *handle, netc_tb_vf_search_criteria_t *sCriteria, netc_tb_vf_rsp_data_t *rsp); +status_t SWT_BridgeSearchVFTableEntry(swt_handle_t *handle, + netc_tb_vf_search_criteria_t *sCriteria, + netc_tb_vf_rsp_data_t *rsp); /*! * @brief Get remaining available entry number (entry size is 24 bytes) of bridge FDB table @@ -1505,6 +1544,17 @@ static inline uint32_t SWT_FMGetTableRemainEntryNum(swt_handle_t *handle) (handle->hw.common->FMITOR & NETC_SW_ENETC_FMITOR_NUM_ENTRIES_MASK); } +/*! + * @brief Get maximum entry number of Frame Modification table + * + * @param handle + * @return uint32_t + */ +static inline uint32_t SWT_FMGetTableMaxEntryNum(swt_handle_t *handle) +{ + return (handle->hw.common->FMITCAPR & NETC_SW_ENETC_FMITCAPR_NUM_ENTRIES_MASK); +} + /*! * @brief Add entry into the Frame Modification table * @@ -1672,10 +1722,10 @@ status_t SWT_FRERConfigESEQRTableEntry(swt_handle_t *handle, netc_tb_eseqr_confi * @return See @ref netc_cmd_error_t */ status_t SWT_FRERQueryESEQRTableEntry(swt_handle_t *handle, - uint32_t entryID, - netc_tb_eseqr_stse_t *statistic, - netc_tb_eseqr_cfge_t *config, - netc_tb_eseqr_srse_t *state); + uint32_t entryID, + netc_tb_eseqr_stse_t *statistic, + netc_tb_eseqr_cfge_t *config, + netc_tb_eseqr_srse_t *state); /*! * @brief Get FRER sequence recorvery table state and statistic @@ -1962,6 +2012,88 @@ status_t SWT_TxETMConfigClassQueue(swt_handle_t *handle, netc_tb_etmcq_config_t */ status_t SWT_TxETMConfigCongestionGroup(swt_handle_t *handle, netc_tb_etmcg_config_t *config); +/*! + * @brief Config Preemption for each port TC (traffic class) + * + * @param handle + * @param portIdx + * @param tcIdx + * @param enable + */ +static inline void SWT_TxTcConfigPreemption(swt_handle_t *handle, + netc_hw_port_idx_t portIdx, + netc_hw_tc_idx_t tcIdx, + const bool enable) +{ + NETC_PORT_Type *base; + + base = handle->hw.ports[portIdx].port; + if (!NETC_PortIsPseudo(base)) + { + NETC_PortConfigTcPreemption(base, tcIdx, enable); + } +} + +/*! + * @brief Get Preemption configuration for each port TC (traffic class) + * + * @param handle + * @param portIdx + * @param tcIdx + * @param enabled + */ +static inline void SWT_TxGetTcPreemption(swt_handle_t *handle, + netc_hw_port_idx_t portIdx, + netc_hw_tc_idx_t tcIdx, + bool *enabled) +{ + NETC_PORT_Type *base; + + base = handle->hw.ports[portIdx].port; + if (!NETC_PortIsPseudo(base)) + { + NETC_PortGetTcPreemption(base, tcIdx, enabled); + } +} + +/*! + * @brief Configure Preemption control configuration for an ethernet MAC + * + * @param handle + * @param portIdx + * @param config + */ +static inline void SWT_TxPortEthMacConfigPreemption(swt_handle_t *handle, + netc_hw_port_idx_t portIdx, + const netc_port_preemption_config *config) +{ + NETC_ETH_LINK_Type *base; + + base = handle->hw.ports[portIdx].eth; + NETC_PortConfigEthMacPreemption(base, config); +} + +/*! + * @brief Get Preemption control configuration from ethernet MAC port + * + * @param handle + * @param portIdx + * @param config + */ +static inline void SWT_TxPortGetEthMacPreemption(swt_handle_t *handle, + netc_hw_port_idx_t portIdx, + netc_port_preemption_config *config, + netc_port_phy_mac_preemption_status_t *status) +{ + NETC_ETH_LINK_Type *base; + + base = handle->hw.ports[portIdx].eth; + + NETC_PortGetPhyMacPreemptionControl(base, config); + + NETC_PortGetPhyMacPreemptionStatus(base, status); +} + /*! @} */ // end of netc_swt_tx #if !(defined(__GNUC__) || defined(__ICCARM__)) #pragma endregion netc_swt_tx @@ -1984,11 +2116,53 @@ status_t SWT_TxETMConfigCongestionGroup(swt_handle_t *handle, netc_tb_etmcg_conf */ status_t SWT_ManagementTxRxConfig(swt_handle_t *handle, ep_handle_t *epHandle, const swt_transfer_config_t *txRxConfig); +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG +/*! + * @brief Transmits a frame on management port. + * + * @param handle The SWT handle + * @param frame The frame descriptor pointer + * @param context Private context provided back on reclaim + * @param opt Tx options. + * @retval status_t + */ +status_t SWT_SendFrame(swt_handle_t *handle, netc_frame_struct_t *frame, void *context, swt_tx_opt *opt); + +/*! + * @brief Wait until the EP Tx ring has completed the transfer. + * + * @note Only call after EP_SendFrame() to do a no-interrupt transfer + * + * @param handle + * @param ring Tx ring. + */ +static inline void SWT_WaitUnitilTxComplete(swt_handle_t *handle, bool enMasquerade, uint8_t ring) +{ + while (handle->epHandle->hw.si->BDR[ring].TBCIR != handle->epHandle->txBdRing[ring].producerIndex) + { + } +} + +/*! + * @brief Reclaim tx descriptors. + * This function is used to update the tx descriptor status. + * For each reclaimed transmit frame the ep_reclaim_cb_t is called. + * + * This is called after being notified of a transmit completion from ISR. + * It runs until there are no more frames to be reclaimed in the BD ring. + * + * @param handle + * @param ring Tx ring. + */ +void SWT_ReclaimTxDescriptor(swt_handle_t *handle, uint8_t ring); + +#else + /*! * @brief Transmits a management frame on a specific port. * * @param handle - * @param ringOrQueue The ring index for Port masquerading or egress port priority/dr for direct enqueue + * @param txArg The ring index for Port masquerading or egress port priority/dr for direct enqueue * @param swtPort The ingress port for Port masquerading or egress for direct enqueue * @param enMasquerade Ture - Use Port masquerading Tx option, False - Use direct enqueue Tx Option * @param frame The frame descriptor pointer @@ -1997,7 +2171,7 @@ status_t SWT_ManagementTxRxConfig(swt_handle_t *handle, ep_handle_t *epHandle, c * @retval status_t */ status_t SWT_SendFrame(swt_handle_t *handle, - swt_mgmt_tx_arg_t ringOrQueue, + swt_mgmt_tx_arg_t txArg, netc_hw_port_idx_t swtPort, bool enMasquerade, netc_frame_struct_t *frame, @@ -2045,6 +2219,19 @@ static inline void SWT_WaitUnitilTxComplete(swt_handle_t *handle, bool enMasquer */ void SWT_ReclaimTxDescriptor(swt_handle_t *handle, bool enMasquerade, uint8_t ring); +/*! + * @brief Receives Switch Transmit Timestamp Reference Response. + * + * @note MUST call SWT_GetRxFrameSize() beforehand to confirm get the kStatus_NETC_RxTsrResp status. + * + * @param handle + * @param tsr Timestamp Reference Response pointer + * @return kStatus_Success Successfully receive Switch Transmit Timestamp Reference Response + * @return kStatus_InvalidArgument No Rx BD ring is available + */ +status_t SWT_GetTimestampRefResp(swt_handle_t *handle, swt_tsr_resp_t *tsr); +#endif + /*! * @brief Receives management frames (host reason not zero) with zero copy * @@ -2076,18 +2263,6 @@ status_t SWT_ReceiveFrame(swt_handle_t *handle, netc_frame_struct_t *frame, netc */ status_t SWT_ReceiveFrameCopy(swt_handle_t *handle, void *buffer, uint32_t length, netc_frame_attr_t *attr); -/*! - * @brief Receives Switch Transmit Timestamp Reference Response. - * - * @note MUST call SWT_GetRxFrameSize() beforehand to confirm get the kStatus_NETC_RxTsrResp status. - * - * @param handle - * @param tsr Timestamp Reference Response pointer - * @return kStatus_Success Successfully receive Switch Transmit Timestamp Reference Response - * @return kStatus_InvalidArgument No Rx BD ring is available - */ -status_t SWT_GetTimestampRefResp(swt_handle_t *handle, swt_tsr_resp_t *tsr); - /*! * brief Gets the size of the pending frame in the specified receive ring buffer. * @@ -2258,6 +2433,86 @@ static inline uint32_t SWT_GetPortTGSListStatus(swt_handle_t *handle, netc_hw_po { return NETC_PortGetTGSListStatus(handle->hw.ports[portIdx].port); } + +/*! + * @brief Set IPV to queue mapping on Switch port + * + * @param handle + * @param portIdx port index + * @param ipvToTC[] queue number of each ipv value + * @return kStatus_Success + */ +static inline status_t SWT_SetPortIPV2QMR(swt_handle_t *handle, netc_hw_port_idx_t portIdx, const uint8_t *ipvToTC) +{ + handle->hw.ports[portIdx].port->PIPV2QMR0 = + NETC_PORT_PIPV2QMR0_IPV7_Q(ipvToTC[7]) | NETC_PORT_PIPV2QMR0_IPV6_Q(ipvToTC[6]) | + NETC_PORT_PIPV2QMR0_IPV5_Q(ipvToTC[5]) | NETC_PORT_PIPV2QMR0_IPV4_Q(ipvToTC[4]) | + NETC_PORT_PIPV2QMR0_IPV3_Q(ipvToTC[3]) | NETC_PORT_PIPV2QMR0_IPV2_Q(ipvToTC[2]) | + NETC_PORT_PIPV2QMR0_IPV1_Q(ipvToTC[1]) | NETC_PORT_PIPV2QMR0_IPV0_Q(ipvToTC[0]); + return kStatus_Success; +} + +/*! + * @brief Enable MAC station move on Switch port + * + * @param handle + * @param portIdx port index + * @param enable Allow MAC station move + * @return kStatus_Success + */ +static inline status_t SWT_EnablePortMacStationMove(swt_handle_t *handle, netc_hw_port_idx_t portIdx, bool enable) +{ + if (enable) + { + handle->hw.ports[portIdx].port->BPCR &= (~NETC_PORT_BPCR_STAMVD_MASK); + } + else + { + handle->hw.ports[portIdx].port->BPCR |= NETC_PORT_BPCR_STAMVD_MASK; + } + + return kStatus_Success; +} + +#if defined(FSL_FEATURE_NETC_HAS_PORT_PSRCR) && FSL_FEATURE_NETC_HAS_PORT_PSRCR +/*! + * @brief Set the port seamless redundancy configuration + * + * Set the port seamless redundancy configuration. + * + * @param handle + * @param portIdx port index + * @param sr netc_swt_port_sr_config_t + * @return kStatus_Success + */ +static inline status_t SWT_SetPortSR(swt_handle_t *handle, netc_hw_port_idx_t portIdx, netc_swt_port_sr_config_t *sr) +{ + handle->hw.ports[portIdx].port->PSRCR = NETC_PORT_PSRCR_ISQG_EID(sr->isqEID) | NETC_PORT_PSRCR_PATHID(sr->pathId) | + NETC_PORT_PSRCR_TX_SQTA(sr->txSqta) | + NETC_PORT_PSRCR_SRC_PORT_FLT(sr->srcPortFlt) | + NETC_PORT_PSRCR_SDFA(sr->sdfa) | NETC_PORT_PSRCR_SR_PORT(sr->srPort); + return kStatus_Success; +} +#endif + +#if defined(FSL_FEATURE_NETC_HAS_PORT_PGCR) && FSL_FEATURE_NETC_HAS_PORT_PGCR +/*! + * @brief Set the port group configuration + * + * Set the port group configuration. + * + * @param handle + * @param portIdx port index + * @param pgid Port Group ID + * @return kStatus_Success + */ +static inline status_t SWT_SetPortGroup(swt_handle_t *handle, netc_hw_port_idx_t portIdx, uint8_t pgid) +{ + handle->hw.ports[portIdx].port->PGCR = NETC_PORT_PGCR_PGID(pgid); + return kStatus_Success; +} +#endif + /*! @} */ // end of netc_swt_stat #if !(defined(__GNUC__) || defined(__ICCARM__)) #pragma endregion netc_swt_stat diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_tag.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_tag.h new file mode 100644 index 0000000000..7312b91ac8 --- /dev/null +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_tag.h @@ -0,0 +1,120 @@ +/* + * Copyright 2024-2025 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_NETC_SWITCH_TAG_H_ +#define FSL_NETC_SWITCH_TAG_H_ + +#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG + +#define NETC_SWITCH_DEFAULT_ETHER_TYPE 0x3AFD + +/*! @brief Switch tag type */ +typedef enum _netc_swt_tag_type +{ + kNETC_TagForward, /*!< Normal frame process. */ + kNETC_TagToPort, /*!< The frame must be transmitted out a specific switch port. */ + kNETC_TagToHost, /*!< Frames that are redirected or copied to the switch management port. */ +} netc_swt_tag_type_t; + +/*! @brief Switch tag subtype */ +typedef enum _netc_swt_tag_subtype +{ + kNETC_TagToPortNoTs = 0, /*!< Normal frame process. */ + kNETC_TagToPortOneStepTs, /*!< The frame must be transmitted out a specific switch port. */ + kNETC_TagToPortTwoStepTs, /*!< Frames that are redirected or copied to the switch management port. */ + kNETC_TagToPortAllTs, /*!< Frames that are redirected or copied to the switch management port. */ + + kNETC_TagToHostNoTs = 0, /*!< Frames that are redirected or copied to the switch management port. */ + kNETC_TagToHostRxTs, /*!< Frames that are redirected or copied to the switch management port. */ + kNETC_TagToHostTxTs, /*!< Frames that are redirected or copied to the switch management port. */ +} netc_swt_tag_subtype_t; + +#pragma pack(1) +/*! @brief Switch tag common part */ +typedef struct _netc_swt_tag_common +{ + uint16_t tpid; /*!< Tag Protocol Identifier to identify the tag as an NXP switch tag. */ + uint16_t subType : 4; /*!< Specific feature is based on tag type. Refer to @netc_swt_tag_subtype_t. */ + uint16_t type : 4; /*!< Tag type. Refer to @netc_swt_tag_type_t. */ + uint16_t qv : 1; /*!< QoS Valid. */ + uint16_t : 1; /*!< Reserved. */ + uint16_t ipv : 3; /*!< Internal Priority Value. */ + uint16_t : 1; /*!< Reserved. */ + uint16_t dr : 2; /*!< Drop Resilience. */ + uint8_t swtId : 3; /*!< Switch ID. */ + uint8_t port : 5; /*!< Switch port. */ +} netc_swt_tag_common_t; + +/*! @brief Switch tag for forward */ +typedef struct _netc_swt_tag_forward +{ + netc_swt_tag_common_t comTag; /*!< Tag Protocol Identifier to identify the tag as an NXP switch tag. */ + uint8_t pm : 1; /*!< Port Masquerading. */ + uint8_t : 7; /*!< Reserved. */ +} netc_swt_tag_forward_t; + +/*! @brief Switch tag for to_port without timestamp */ +typedef struct _netc_swt_tag_port_no_ts +{ + netc_swt_tag_common_t comTag; /*!< Tag Protocol Identifier to identify the tag as an NXP switch tag. */ + uint8_t : 8; /*!< Reserved. */ +} netc_swt_tag_port_no_ts_t; + +/*! @brief Switch tag for to_port with one-step timestamp */ +typedef struct _netc_swt_tag_port_one_step_ts +{ + netc_swt_tag_common_t comTag; /*!< Tag Protocol Identifier to identify the tag as an NXP switch tag. */ + uint8_t : 8; /*!< Reserved. */ + uint32_t timestamp; /*!< Timestamp. */ +} netc_swt_tag_port_one_step_ts_t; + +/*! @brief Switch tag for to_port without two-step timestamp */ +typedef struct _netc_swt_tag_port_two_step_ts +{ + netc_swt_tag_common_t comTag; /*!< Tag Protocol Identifier to identify the tag as an NXP switch tag. */ + uint8_t tsReqId : 4; /*!< Timestamp Request Identifier. */ + uint8_t : 4; /*!< Reserved. */ +} netc_swt_tag_port_two_step_ts_t; + +/*! @brief Switch tag for to_port with all timestamps */ +typedef struct _netc_swt_tag_port_all_ts +{ + netc_swt_tag_common_t comTag; /*!< Tag Protocol Identifier to identify the tag as an NXP switch tag. */ + uint8_t tsReqId : 4; /*!< Timestamp Request Identifier. */ + uint8_t : 4; /*!< Reserved. */ + uint32_t timestamp; /*!< Timestamp. */ +} netc_swt_tag_port_all_ts_t; + +/*! @brief Switch tag for to_host */ +typedef struct _netc_swt_tag_host +{ + netc_swt_tag_common_t comTag; /*!< Tag Protocol Identifier to identify the tag as an NXP switch tag. */ + uint16_t : 4; /*!< Reserved. */ + uint16_t hostReason : 4; /*!< Host reason. */ +} netc_swt_tag_host_t; + +/*! @brief Switch tag for to_host with timestamp */ +typedef struct _netc_swt_tag_host_rx_ts +{ + netc_swt_tag_common_t comTag; /*!< Tag Protocol Identifier to identify the tag as an NXP switch tag. */ + uint16_t : 4; /*!< Reserved. */ + uint16_t hostReason : 4; /*!< Host reason. */ + uint64_t timestamp; /*!< Timestamp. */ +} netc_swt_tag_host_rx_ts_t; + +/*! @brief Switch tag for to_host with timestamp */ +typedef struct _netc_swt_tag_host_tx_ts +{ + netc_swt_tag_common_t comTag; /*!< Tag Protocol Identifier to identify the tag as an NXP switch tag. */ + uint16_t tsReqId : 4; /*!< Timestamp Request Identifier. */ + uint16_t hostReason : 4; /*!< Host reason. */ + uint64_t timestamp; /*!< Timestamp. */ +} netc_swt_tag_host_tx_ts_t; +#pragma pack() + +#endif /* FSL_FEATURE_NETC_HAS_SWITCH_TAG */ + +#endif /* FSL_NETC_SWITCH_TAG_H_ */ diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_timer.c b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_timer.c index 732a6e65c2..c22b7cba13 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_timer.c +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_timer.c @@ -70,8 +70,8 @@ status_t NETC_TimerInit(netc_timer_handle_t *handle, const netc_timer_config_t * /* Initialize the handle. */ NETC_TimerInitHandle(handle); - handle->entryNum = config->entryNum; - handle->timerFreq = config->refClkHz; + handle->entryNum = config->entryNum; + handle->timerFreq = config->refClkHz; /* Reset this function */ handle->hw.func->PCI_CFC_PCIE_DEV_CTL |= ENETC_PCI_TYPE0_PCI_CFC_PCIE_DEV_CTL_INIT_FLR_MASK; @@ -276,10 +276,10 @@ void NETC_TimerConfigureExtPulseTrig(netc_timer_handle_t *handle, handle->hw.base->TMR_CTRL &= ~clear; handle->hw.base->TMR_CTRL |= control; - clear = (extTrigId == kNETC_TimerExtTrig1) ? - (ENETC_PF_TMR_TMR_TEMASK_ETS1EN_MASK | ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN_MASK | + clear = (extTrigId == kNETC_TimerExtTrig1) ? + (ENETC_PF_TMR_TMR_TEMASK_ETS1EN_MASK | ENETC_PF_TMR_TMR_TEMASK_ETS1_THREN_MASK | ENETC_PF_TMR_TMR_TEMASK_ETS1_OVEN_MASK) : - (ENETC_PF_TMR_TMR_TEMASK_ETS2EN_MASK | ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN_MASK | + (ENETC_PF_TMR_TMR_TEMASK_ETS2EN_MASK | ENETC_PF_TMR_TMR_TEMASK_ETS2_THREN_MASK | ENETC_PF_TMR_TMR_TEMASK_ETS2_OVEN_MASK); control = (extTrigId == kNETC_TimerExtTrig1) ? (ENETC_PF_TMR_TMR_TEMASK_ETS1EN(extTrig->enableTsAvailInterrupt) | @@ -321,7 +321,7 @@ status_t NETC_TimerReadExtPulseCaptureTime(netc_timer_handle_t *handle, else { timeLow = handle->hw.base->TMR_ETTSN[1].TMR_ETTS_L; - timeHigh = handle->hw.base->TMR_ETTSN[1].TMR_ETTS_H; + timeHigh = handle->hw.base->TMR_ETTSN[1].TMR_ETTS_H; } *nanosecond = ((uint64_t)timeHigh << 32U) + timeLow; result = kStatus_Success; @@ -334,7 +334,8 @@ static void __NETC_TimerGetCurrentTime(ENETC_PF_TMR_Type *base, uint64_t *nanose uint32_t timeLow, timeHigh[2]; timeHigh[0] = base->TMR_CUR_TIME_H; - do { + do + { timeHigh[1] = timeHigh[0]; timeLow = base->TMR_CUR_TIME_L; timeHigh[0] = base->TMR_CUR_TIME_H; @@ -345,13 +346,17 @@ static void __NETC_TimerGetCurrentTime(ENETC_PF_TMR_Type *base, uint64_t *nanose void NETC_TimerGetTime(ENETC_PF_TMR_Type *base, uint64_t *nanosecond) { - if ((base->TMR_CTRL & ENETC_PF_TMR_TMR_CTRL_TE_MASK) != 0U) { + if ((base->TMR_CTRL & ENETC_PF_TMR_TMR_CTRL_TE_MASK) != 0U) + { __NETC_TimerGetCurrentTime(base, nanosecond); - } else { + } + else + { uint32_t timeLow, timeHigh[2]; timeHigh[0] = base->TMR_DEF_CNT_H; - do { + do + { timeHigh[1] = timeHigh[0]; timeLow = base->TMR_DEF_CNT_L; timeHigh[0] = base->TMR_DEF_CNT_H; diff --git a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_timer.h b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_timer.h index 9972700ded..444fbb59a1 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_timer.h +++ b/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_timer.h @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 NXP + * Copyright 2021-2023, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -77,13 +77,13 @@ typedef enum _netc_timer_irq_flags ENETC_PF_TMR_TMR_TEVENT_ETS2_THREN_MASK, /*!< External trigger 2 timestamp FIFO threshold hit interrupt. */ kNETC_TimerExtTrig1TsAvailIrqFlag = - ENETC_PF_TMR_TMR_TEVENT_ETS1EN_MASK, /*!< External trigger 1 new timestamp available interrupt. */ + ENETC_PF_TMR_TMR_TEVENT_ETS1EN_MASK, /*!< External trigger 1 new timestamp available interrupt. */ kNETC_TimerExtTrig2TsAvailIrqFlag = - ENETC_PF_TMR_TMR_TEVENT_ETS2EN_MASK, /*!< External trigger 2 new timestamp available interrupt. */ + ENETC_PF_TMR_TMR_TEVENT_ETS2EN_MASK, /*!< External trigger 2 new timestamp available interrupt. */ kNETC_TimerExtTrig1OverflowIrqFlag = - ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN_MASK, /*!< External trigger 1 timestamp FIFO overflow interrupt. */ + ENETC_PF_TMR_TMR_TEVENT_ETS1_OVEN_MASK, /*!< External trigger 1 timestamp FIFO overflow interrupt. */ kNETC_TimerExtTrig2OverflowIrqFlag = - ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN_MASK, /*!< External trigger 2 timestamp FIFO overflow interrupt. */ + ENETC_PF_TMR_TMR_TEVENT_ETS2_OVEN_MASK, /*!< External trigger 2 timestamp FIFO overflow interrupt. */ } netc_timer_irq_flags_t; typedef struct _netc_timer_handle netc_timer_handle_t; diff --git a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c index 9010a51149..a0c2e429d9 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c +++ b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c @@ -1,5 +1,5 @@ /* - * Copyright 2022-2024 NXP + * Copyright 2022-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,8 +25,7 @@ NETC_SW_ENETC_ISIDKC0CR0_IPCPP(x.ipcpp) | NETC_SW_ENETC_ISIDKC0CR0_IVIDP(x.ividp) | \ NETC_SW_ENETC_ISIDKC0CR0_OPCPP(x.opcpp) | NETC_SW_ENETC_ISIDKC0CR0_OVIDP(x.ovidp) | \ NETC_SW_ENETC_ISIDKC0CR0_SMACP(x.smacp) | NETC_SW_ENETC_ISIDKC0CR0_DMACP(x.dmacp) | \ - NETC_SW_ENETC_ISIDKC0CR0_PORTP(x.portp) | \ - NETC_SW_ENETC_ISIDKC0CR0_VALID(x.valid)) + NETC_SW_ENETC_ISIDKC0CR0_PORTP(x.portp) | NETC_SW_ENETC_ISIDKC0CR0_VALID(x.valid)) #endif #define NETC_KC_PAYLOAD(x) \ @@ -309,8 +308,8 @@ status_t NETC_QueryIPFTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, n cmdBd.req.resLength = sizeof(netc_tb_ipf_rsp_data_t); cmdBd.req.tableId = kNETC_IPFTable; cmdBd.req.cmd = kNETC_QueryEntry; - cmdBd.req.accessType = kNETC_EntryIDMatch; - status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); + cmdBd.req.accessType = kNETC_EntryIDMatch; + status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); if (kStatus_Success == status) { config->keye = handle->buffer->ipf.response.keye; @@ -416,8 +415,8 @@ status_t NETC_QueryISITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, n cmdBd.req.resLength = sizeof(netc_tb_isi_rsp_data_t); cmdBd.req.tableId = kNETC_ISITable; cmdBd.req.cmd = kNETC_QueryEntry; - cmdBd.req.accessType = kNETC_EntryIDMatch; - status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); + cmdBd.req.accessType = kNETC_EntryIDMatch; + status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); if (kStatus_Success == status) { if (0U != cmdBd.resp.numMatched) @@ -434,7 +433,9 @@ status_t NETC_QueryISITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, n return status; } -status_t NETC_QueryISITableEntryWithKey(netc_cbdr_handle_t *handle, netc_tb_isi_keye_t *keye, netc_tb_isi_rsp_data_t *rsp) +status_t NETC_QueryISITableEntryWithKey(netc_cbdr_handle_t *handle, + netc_tb_isi_keye_t *keye, + netc_tb_isi_rsp_data_t *rsp) { netc_cmd_bd_t cmdBd = {0}; status_t status = kStatus_Success; @@ -448,7 +449,7 @@ status_t NETC_QueryISITableEntryWithKey(netc_cbdr_handle_t *handle, netc_tb_isi_ cmdBd.req.tableId = kNETC_ISITable; cmdBd.req.cmd = kNETC_QueryEntry; cmdBd.req.accessType = kNETC_ExactKeyMatch; - status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); + status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); if (kStatus_Success == status) { if (0U != cmdBd.resp.numMatched) @@ -519,14 +520,14 @@ status_t NETC_QueryISTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, ne cmdBd.req.resLength = sizeof(netc_tb_is_rsp_data_t); cmdBd.req.tableId = kNETC_ISTable; cmdBd.req.cmd = kNETC_QueryEntry; - cmdBd.req.accessType = kNETC_EntryIDMatch; - status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); + cmdBd.req.accessType = kNETC_EntryIDMatch; + status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); if (kStatus_Success == status) { if (0U != cmdBd.resp.numMatched) { config->entryID = handle->buffer->is.response.entryID; - config->cfge = handle->buffer->is.response.cfge; + config->cfge = handle->buffer->is.response.cfge; } else { @@ -679,10 +680,12 @@ status_t NETC_GetISCStatistic(netc_cbdr_handle_t *handle, uint32_t entryID, netc if (kStatus_Success == status) { *statistic = handle->buffer->isc.response.stse; -#if (defined(FSL_FEATURE_NETC_HAS_ERRATA_052134) && FSL_FEATURE_NETC_HAS_ERRATA_052134) - /* ERR052134: The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is bit 200 or the offset within - the entire Ingress Stream Count Table Response Data Buffer format is bit 232. Starting offset is 8-bits. */ - statistic->sgDropCount >>= 8U; +#if (defined(FSL_FEATURE_NETC_HAS_ERRATA_052206) && FSL_FEATURE_NETC_HAS_ERRATA_052206) + /* ERR052206: The actual offset of the SG_DROP_COUNT in the Ingress Stream Count Table STSE_DATA element is bit + 199 or the offset within the entire Ingress Stream Count Table Response Data Buffer format is bit 231. + Starting offset from defined is 7-bits. */ + statistic->sgDropCount >>= 7U; + statistic->sgDropCount += ((statistic->res3 & 0x7FU) << 25U); #endif } return status; @@ -734,6 +737,36 @@ status_t NETC_AddOrUpdateSGITableEntry(netc_cbdr_handle_t *handle, netc_tb_sgi_c return NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); } +status_t NETC_ResetIRXOEXSGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID) +{ + status_t status; + netc_cmd_bd_t cmdBd = {0}; + (void)memset(handle->buffer, 0, sizeof(netc_tb_sgi_req_data_t)); + handle->buffer->sgi.request.entryID = entryID; + handle->buffer->sgi.request.commonHeader.updateActions = (uint16_t)kNETC_SGISgisEUpdate; + handle->buffer->sgi.request.commonHeader.queryActions = 0U; + cmdBd.req.addr = (uintptr_t)handle->buffer; + cmdBd.req.reqLength = sizeof(netc_tb_sgi_req_data_t); + cmdBd.req.resLength = 0U; + cmdBd.req.tableId = kNETC_SGITable; + cmdBd.req.cmd = kNETC_UpdateEntry; + cmdBd.req.accessType = kNETC_EntryIDMatch; + status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); + if (kStatus_Success == status) + { + if (cmdBd.resp.numMatched == 0U) + { + status = kStatus_NETC_NotFound; + } + else + { + /* Intentional empty */ + } + } + + return status; +} + status_t NETC_DelSGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID) { netc_cmd_bd_t cmdBd = {0}; @@ -755,7 +788,7 @@ status_t NETC_GetSGIState(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_ { netc_cmd_bd_t cmdBd = {0}; status_t status = kStatus_Success; - (void)memset(handle->buffer, 0, sizeof(netc_tb_sgi_rsp_data_t)); + (void)memset(handle->buffer, 0, sizeof(netc_tb_sgi_req_data_t)); handle->buffer->sgi.request.entryID = entryID; handle->buffer->sgi.request.commonHeader.updateActions = 0U; handle->buffer->sgi.request.commonHeader.queryActions = 0U; @@ -773,7 +806,7 @@ status_t NETC_GetSGIState(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_ return status; } -status_t NETC_QuerySGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgi_rsp_data_t *rsp) +status_t NETC_QuerySGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgi_config_t *cfg) { netc_cmd_bd_t cmdBd = {0}; status_t status = kStatus_Success; @@ -792,7 +825,9 @@ status_t NETC_QuerySGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, n { if (cmdBd.resp.numMatched != 0U) { - *rsp = handle->buffer->sgi.response; + cfg->cfge = handle->buffer->sgi.response.cfge; + cfg->icfge = handle->buffer->sgi.response.icfge; + cfg->acfge = handle->buffer->sgi.response.acfge; } else { @@ -936,7 +971,7 @@ status_t NETC_AddOrUpdateRPTableEntry(netc_cbdr_handle_t *handle, netc_tb_rp_con /* Only support Entry ID Match */ cmdBd.req.accessType = kNETC_EntryIDMatch; - status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); + status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); if (kStatus_Success == status) { if ((cmd == kNETC_AddEntry) && (cmdBd.resp.numMatched > 0U)) @@ -972,7 +1007,7 @@ status_t NETC_ResetMRRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID) /* Only support Entry ID Match */ cmdBd.req.accessType = kNETC_EntryIDMatch; - status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); + status = NETC_CmdBDSendCommand(handle->base, handle->cmdr, &cmdBd, kNETC_NtmpV2_0); if (kStatus_Success == status) { if (cmdBd.resp.numMatched == 0U) @@ -1007,7 +1042,7 @@ status_t NETC_DelRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID) status_t NETC_QueryRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_rp_rsp_data_t *rsp) { netc_cmd_bd_t cmdBd = {0}; - status_t status = kStatus_Success; + status_t status = kStatus_Success; (void)memset(handle->buffer, 0, sizeof(netc_tb_rp_rsp_data_t)); handle->buffer->rp.request.entryID = entryID; handle->buffer->rp.request.commonHeader.updateActions = 0; @@ -1025,7 +1060,7 @@ status_t NETC_QueryRPTableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, ne { *rsp = handle->buffer->rp.response; } - else + else { status = kStatus_NETC_NotFound; } diff --git a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.h b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.h index 11be67aeb4..267ec0be7c 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.h +++ b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.h @@ -1,5 +1,5 @@ /* - * Copyright 2021-2024 NXP + * Copyright 2021-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,7 @@ */ /*! @brief MSIX table address offset. */ -#define NETC_MSIX_TABLE_OFFSET (0x10000U) +#define NETC_MSIX_TABLE_OFFSET (0x10000U) /*! @brief MSIX PBA address offset. */ #define NETC_MSIX_TABLE_PBA_OFFSET (0x800U) @@ -99,11 +99,11 @@ typedef struct _netc_timer_hw /*! @brief Register group for both EMDIO and port external MDIO. */ typedef struct _netc_mdio_hw { - __IO uint32_t EMDIO_CFG; /*!< External MDIO configuration register, offset: 0x1C00 */ - __IO uint32_t EMDIO_CTL; /*!< External MDIO interface control register, offset: 0x1C04 */ - __IO uint32_t EMDIO_DATA; /*!< External MDIO interface data register, offset: 0x1C08 */ - __IO uint32_t EMDIO_ADDR; /*!< External MDIO register address register, offset: 0x1C0C */ - __I uint32_t EMDIO_STAT; /*!< External MDIO status register, offset: 0x1C10 */ + __IO uint32_t EMDIO_CFG; /*!< External MDIO configuration register, offset: 0x1C00 */ + __IO uint32_t EMDIO_CTL; /*!< External MDIO interface control register, offset: 0x1C04 */ + __IO uint32_t EMDIO_DATA; /*!< External MDIO interface data register, offset: 0x1C08 */ + __IO uint32_t EMDIO_ADDR; /*!< External MDIO register address register, offset: 0x1C0C */ + __I uint32_t EMDIO_STAT; /*!< External MDIO status register, offset: 0x1C10 */ uint8_t RESERVED_1[12]; __IO uint32_t PHY_STATUS_CFG; /*!< PHY status configuration register, offset: 0x1C20 */ __IO uint32_t PHY_STATUS_CTL; /*!< PHY status control register, offset: 0x1C24 */ @@ -128,8 +128,8 @@ typedef struct _netc_mdio_hw /*! @brief Register group for SI/Switch command bd ring */ typedef struct _netc_cbdr_hw { - __IO uint32_t CBDRMR; /*!< Command BDR mode register. */ - __I uint32_t CBDRSR; /*!< Command BDR status register. */ + __IO uint32_t CBDRMR; /*!< Command BDR mode register. */ + __I uint32_t CBDRSR; /*!< Command BDR status register. */ uint8_t RESERVED_0[8]; __IO uint32_t CBDRBAR0; /*!< Command BDR base address register 0 */ __IO uint32_t CBDRBAR1; /*!< Command BDR base address register 1 */ @@ -379,7 +379,9 @@ status_t NETC_QueryISITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, n * @return status_t * @return See @ref netc_cmd_error_t */ -status_t NETC_QueryISITableEntryWithKey(netc_cbdr_handle_t *handle, netc_tb_isi_keye_t *keye, netc_tb_isi_rsp_data_t *rsp); +status_t NETC_QueryISITableEntryWithKey(netc_cbdr_handle_t *handle, + netc_tb_isi_keye_t *keye, + netc_tb_isi_rsp_data_t *rsp); /*! * @brief Add or update entry in Ingress Stream table @@ -497,6 +499,16 @@ status_t NETC_ResetISCStatistic(netc_cbdr_handle_t *handle, uint32_t entryID); */ status_t NETC_AddOrUpdateSGITableEntry(netc_cbdr_handle_t *handle, netc_tb_sgi_config_t *config, bool isAdd); +/*! + * @brief Reset IRX and OEX flags in stream gate instance entry + * + * @param handle + * @param entryID + * @return status_t + * @return See @ref netc_cmd_error_t + */ +status_t NETC_ResetIRXOEXSGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID); + /*! * @brief Delete entry in the stream gate instance table * @@ -523,11 +535,11 @@ status_t NETC_GetSGIState(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_ * * @param handle * @param entryID - * @param rsp + * @param config * @return status_t * @return See @ref netc_cmd_error_t */ -status_t NETC_QuerySGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgi_rsp_data_t *rsp); +status_t NETC_QuerySGITableEntry(netc_cbdr_handle_t *handle, uint32_t entryID, netc_tb_sgi_config_t *config); /*! * @brief Add entry into Stream Gate Control List Table diff --git a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_port.c b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_port.c index 85fc6d0187..42dd860226 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_port.c +++ b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_port.c @@ -1,5 +1,5 @@ /* - * Copyright 2021-2024 NXP + * Copyright 2021-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -60,6 +60,14 @@ status_t NETC_PortSetMII(NETC_ETH_LINK_Type *base, netc_hw_mii_speed_t speed, netc_hw_mii_duplex_t duplex) { +#if (defined(FSL_FEATURE_NETC_HAS_ERRATA_052167) && FSL_FEATURE_NETC_HAS_ERRATA_052167) + /* ERR052167: Actual MAC Tx IPG is longer than configured when transmitting back-to-back packets in MII half duplex + mode by approximately 15 extra bytes. For example, when configured for IPG=12, the actual IPG will be + approximately 27. The net result is that maximum throughput will be reduced also in the absence of half-duplex + collision/retry events. When using MII protocol, using full-duplex mode is recommended instead of half-duplex. If + using MII half-duplex mode, additional bandwidth loss should be expected and accounted for due to extended IPG. */ +#endif + uint32_t reg = base->PM0_IF_MODE; /* Set MAC interface mode */ @@ -99,13 +107,17 @@ status_t NETC_PortSetMII(NETC_ETH_LINK_Type *base, reg |= NETC_ETH_LINK_PM0_IF_MODE_HD(duplex != kNETC_MiiFullDuplex); } } - else /* kNETC_GmiiMode, force 1Gbps and full speed */ + else if (miiMode == kNETC_GmiiMode) /* kNETC_GmiiMode, force 1Gbps and full speed */ { if ((speed < kNETC_MiiSpeed1000M) || (duplex != kNETC_MiiFullDuplex)) { return kStatus_InvalidArgument; } } + else + { + /* Avoid MISRA 2012 rule 15.7 */ + } base->PM0_IF_MODE = reg; base->PM1_IF_MODE = reg; @@ -179,9 +191,7 @@ status_t NETC_PortConfigEthMac(NETC_ETH_LINK_Type *base, const netc_port_ethmac_ base->PM0_IF_MODE = reg; base->PM1_IF_MODE = reg; - base->MAC_MERGE_MMCSR = NETC_ETH_LINK_MAC_MERGE_MMCSR_VT(config->mergeVerifyTime) | - NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS(!config->enMergeVerify) | - NETC_ETH_LINK_MAC_MERGE_MMCSR_ME(config->preemptMode); + NETC_PortConfigEthMacPreemption(base, &config->PreemptionConfig); #if !(defined(FSL_FEATURE_NETC_HAS_ERRATA_051255) && FSL_FEATURE_NETC_HAS_ERRATA_051255) reg = NETC_ETH_LINK_PM0_SINGLE_STEP_CH(config->enChUpdate) | @@ -212,8 +222,9 @@ status_t NETC_PortConfigEthMac(NETC_ETH_LINK_Type *base, const netc_port_ethmac_ } #if defined(FSL_FEATURE_NETC_HAS_ERRATA_051994) && FSL_FEATURE_NETC_HAS_ERRATA_051994 - /* ERRATA051994: The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. and as a result may transmit frames before the PHY - has woken up from low power state. Such frames would be lost. Disable autonomous low power idle on Tx in case this issue. */ + /* ERRATA051994: The NETC does not always obey the wakeup time in PMn_LPWAKETIMER. and as a result may transmit + frames before the PHY has woken up from low power state. Such frames would be lost. Disable autonomous low power + idle on Tx in case this issue. */ if (config->txSleepTimeCycleEEE != 0U) { return kStatus_NETC_Unsupported; @@ -258,7 +269,10 @@ void NETC_ClearPortMacInterruptFlags(NETC_ETH_LINK_Type *base, netc_port_phy_mac } } -void NETC_EnablePortMacInterrupts(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, uint32_t mask, bool enable) +void NETC_EnablePortMacInterrupts(NETC_ETH_LINK_Type *base, + netc_port_phy_mac_type_t macType, + uint32_t mask, + bool enable) { if (macType == kNETC_ExpressMAC) { @@ -376,7 +390,9 @@ void NETC_PortGetPhyMacTxStatistic(NETC_ETH_LINK_Type *base, /* ERRATA051711: MAC statistic counters TEOCT and TOCT are inaccurate after Pause frames are transmitted with flexible preamble enabled (PM0_TX_IPG_PREAMBLE[FLEX_PREAMBLE_EN] = 1) and flexible preamble count (PM0_TX_IPG_PREAMBLE[FLEX_PREAMBLE_CNT]) set to less than 7. */ - uint32_t flexPreambleCnt = (base->PM0_TX_IPG_PREAMBLE & NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_MASK) >> NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_SHIFT; + uint32_t flexPreambleCnt = + (base->PM0_TX_IPG_PREAMBLE & NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_MASK) >> + NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_CNT_SHIFT; if ((base->PM0_TX_IPG_PREAMBLE & NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_MASK) != 0U) { statistic->totalOctet = base->PM0_TEOCTN - base->PM0_TXPFN * ((uint64_t)7U - flexPreambleCnt); @@ -391,13 +407,14 @@ void NETC_PortGetPhyMacTxStatistic(NETC_ETH_LINK_Type *base, statistic->totalOctet = base->PM0_TEOCTN; statistic->validOctet = base->PM0_TOCTN; #endif - statistic->pauseFrame = base->PM0_TXPFN; + statistic->pauseFrame = base->PM0_TXPFN; #if defined(FSL_FEATURE_NETC_HAS_ERRATA_051710) && FSL_FEATURE_NETC_HAS_ERRATA_051710 - /* ERRATA051710: After one or more late collision or excessive collision events, counters PMa_TOCTn and PMa_TFRMn will be higher than - expected. The accurate value cannot be recovered for PMa_TOCTn, but PMa_TRFMn can be recovered as follows formula. */ - statistic->validFrame = base->PM0_TFRMN - base->PM0_TLCOLN - base->PM0_TECOLN; + /* ERRATA051710: After one or more late collision or excessive collision events, counters PMa_TOCTn and + PMa_TFRMn will be higher than expected. The accurate value cannot be recovered for PMa_TOCTn, but PMa_TRFMn + can be recovered as follows formula. */ + statistic->validFrame = base->PM0_TFRMN - base->PM0_TLCOLN - base->PM0_TECOLN; #else - statistic->validFrame = base->PM0_TFRMN; + statistic->validFrame = base->PM0_TFRMN; #endif statistic->vlanFrame = base->PM0_TVLANN; statistic->unicastFrame = base->PM0_TUCAN; @@ -415,15 +432,16 @@ void NETC_PortGetPhyMacTxStatistic(NETC_ETH_LINK_Type *base, } else if (macType == kNETC_PreemptableMAC) { - statistic->totalOctet = base->PM1_TEOCTN; - statistic->validOctet = base->PM1_TOCTN; - statistic->pauseFrame = base->PM1_TXPFN; + statistic->totalOctet = base->PM1_TEOCTN; + statistic->validOctet = base->PM1_TOCTN; + statistic->pauseFrame = base->PM1_TXPFN; #if defined(FSL_FEATURE_NETC_HAS_ERRATA_051710) && FSL_FEATURE_NETC_HAS_ERRATA_051710 - /* ERRATA051710: After one or more late collision or excessive collision events, counters PMa_TOCTn and PMa_TFRMn will be higher than - expected. The accurate value cannot be recovered for PMa_TOCTn, but PMa_TRFMn can be recovered as follows formula. */ - statistic->validFrame = base->PM1_TFRMN - base->PM1_TLCOLN - base->PM1_TECOLN; + /* ERRATA051710: After one or more late collision or excessive collision events, counters PMa_TOCTn and + PMa_TFRMn will be higher than expected. The accurate value cannot be recovered for PMa_TOCTn, but PMa_TRFMn + can be recovered as follows formula. */ + statistic->validFrame = base->PM1_TFRMN - base->PM1_TLCOLN - base->PM1_TECOLN; #else - statistic->validFrame = base->PM1_TFRMN; + statistic->validFrame = base->PM1_TFRMN; #endif statistic->vlanFrame = base->PM1_TVLANN; statistic->unicastFrame = base->PM1_TUCAN; @@ -479,7 +497,7 @@ void NETC_PortGetPhyMacRxStatistic(NETC_ETH_LINK_Type *base, statistic->total1523ToMaxBPacket = base->PM0_R1523XN; statistic->controlPacket = base->PM0_RCNPN; #if defined(NETC_ETH_LINK_PM0_RMIN63N_RMIN63n_MASK) - statistic->rxMinPacket = base->PM0_RMIN63N; + statistic->rxMinPacket = base->PM0_RMIN63N; #endif } else if (macType == kNETC_PreemptableMAC) @@ -502,7 +520,7 @@ void NETC_PortGetPhyMacRxStatistic(NETC_ETH_LINK_Type *base, statistic->total1523ToMaxBPacket = base->PM1_R1523XN; statistic->controlPacket = base->PM1_RCNPN; #if defined(NETC_ETH_LINK_PM1_RMIN63N_RMIN63n_MASK) - statistic->rxMinPacket = base->PM1_RMIN63N; + statistic->rxMinPacket = base->PM1_RMIN63N; #endif } else @@ -564,17 +582,17 @@ void NETC_PortGetPhyMacPreemptionStatistic(NETC_ETH_LINK_Type *base, { statistic->rxReassembledFrame = base->MAC_MERGE_MMFAOCR; #if defined(FSL_FEATURE_NETC_HAS_ERRATA_051707) && FSL_FEATURE_NETC_HAS_ERRATA_051707 - /* ERRATA051707: The host that is reading MAC_MERGE_MMFAECR register should check status of PM1_RFCS. If the PM1_RFCS indicates no - error then MAC_MERGE_MMFAECR is valid and can be used if on other hand there is an error reported in PM1_RFCS register - then MAC_MERGE_MMFAECR might be incorrect and should be treated accordingly. */ + /* ERRATA051707: The host that is reading MAC_MERGE_MMFAECR register should check status of PM1_RFCS. If the + PM1_RFCS indicates no error then MAC_MERGE_MMFAECR is valid and can be used if on other hand there is an error + reported in PM1_RFCS register then MAC_MERGE_MMFAECR might be incorrect and should be treated accordingly. */ statistic->rxReassembledError = (base->PM1_RFCSN == 0U) ? base->MAC_MERGE_MMFAECR : 0U; #else statistic->rxReassembledError = base->MAC_MERGE_MMFAECR; #endif - statistic->rxMPacket = base->MAC_MERGE_MMFCRXR; - statistic->rxSMDError = base->MAC_MERGE_MMFSECR; - statistic->txPreemptionReq = base->MAC_MERGE_MMHCR; - statistic->txMPacket = base->MAC_MERGE_MMFCTXR; + statistic->rxMPacket = base->MAC_MERGE_MMFCRXR; + statistic->rxSMDError = base->MAC_MERGE_MMFSECR; + statistic->txPreemptionReq = base->MAC_MERGE_MMHCR; + statistic->txMPacket = base->MAC_MERGE_MMFCTXR; } #if !(defined(FSL_FEATURE_NETC_HAS_NO_SWITCH) && FSL_FEATURE_NETC_HAS_NO_SWITCH) @@ -612,14 +630,16 @@ status_t NETC_PortConfigTxIpgPreamble(NETC_ETH_LINK_Type *base, uint8_t preamble assert((preambleCnt >= 1U) && (preambleCnt <= 7U)); assert((ipgLen >= 4U) && (ipgLen <= 24U)); #if (defined(FSL_FEATURE_NETC_HAS_ERRATA_052129) && FSL_FEATURE_NETC_HAS_ERRATA_052129) - /* ERR052129: The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set to the minimum value. - As a result, frames may be lost, or partially received with a CRC error (e.g. if there is a data octet later in the frame that matches SFD). - When connecting NETC MAC to NETC MAC, for IPG_LEN=4, the minimum supported preamble is 2 bytes. When connecting NETC MAC to another device - that supports shorter-than standard IPG and preamble, ensure that the minimum IPG + preamble is 6 octets. */ + /* ERR052129: The receiving NETC MAC cannot reliably detect the frame when IPG length and flexiable preamble are set + to the minimum value. As a result, frames may be lost, or partially received with a CRC error (e.g. if there is a + data octet later in the frame that matches SFD). When connecting NETC MAC to NETC MAC, for IPG_LEN=4, the minimum + supported preamble is 2 bytes. When connecting NETC MAC to another device that supports shorter-than standard IPG + and preamble, ensure that the minimum IPG + preamble is 6 octets. */ assert((ipgLen + preambleCnt) >= 6U); #endif -#if defined(NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_MASK) && defined(NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_MASK) +#if defined(NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_MASK) && \ + defined(NETC_ETH_LINK_PM1_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN_MASK) bool enable = (preambleCnt < 7U) ? true : false; base->PM0_TX_IPG_PREAMBLE = NETC_ETH_LINK_PM0_TX_IPG_PREAMBLE_FLEX_PREAMBLE_EN(enable) | diff --git a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_port.h b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_port.h index dbabb86dd4..6302023361 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_port.h +++ b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_port.h @@ -1,5 +1,5 @@ /* - * Copyright 2021-2024 NXP + * Copyright 2021-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,23 +25,25 @@ typedef enum _netc_port_intr_flags { - kNETC_TxEmptyFlag = NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY_MASK, /*!< Tx FIFO empty flag. */ - kNETC_RxEmptyFlag = NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY_MASK, /*!< Rx FIFO empty flag. */ - kNETC_TxOverflowFlag = NETC_ETH_LINK_PM0_IEVENT_TX_OVFL_MASK, /*!< Tx overflow flag. */ - kNETC_TxUnderflowFlag = NETC_ETH_LINK_PM0_IEVENT_TX_UNFL_MASK, /*!< Tx underflow flag. */ - kNETC_RxOverflowFlag = NETC_ETH_LINK_PM0_IEVENT_RX_OVFL_MASK, /*!< Rx overflow flag. */ - kNETC_MagicPacketFlag = NETC_ETH_LINK_PM0_IEVENT_MGI_MASK, /*!< Magic packet detection indication flag. */ - kNETC_TxClkStopFlag = NETC_ETH_LINK_PM0_IEVENT_TX_CSD_MASK, /*!< Tx clock stop detection flag. */ - kNETC_RxClkStopFlag = NETC_ETH_LINK_PM0_IEVENT_RX_CSD_MASK, /*!< Rx clock stop detection flag. */ - kNETC_SpeedDuplexChangeFlag = NETC_ETH_LINK_PM0_IEVENT_SPD_DUP_MASK, /*!< Speed/Duplex Change flag */ - kNETC_MacMergeSMDErrFlag = NETC_ETH_LINK_PM0_IEVENT_MRG_SERR_MASK, /*!< MAC merge frame SMD error received event flag */ - kNETC_MacMergeAssemblyErrFlag = NETC_ETH_LINK_PM0_IEVENT_MRG_AERR_MASK, /*!< MAC merge frame assembly error event flag */ + kNETC_TxEmptyFlag = NETC_ETH_LINK_PM0_IEVENT_TX_EMPTY_MASK, /*!< Tx FIFO empty flag. */ + kNETC_RxEmptyFlag = NETC_ETH_LINK_PM0_IEVENT_RX_EMPTY_MASK, /*!< Rx FIFO empty flag. */ + kNETC_TxOverflowFlag = NETC_ETH_LINK_PM0_IEVENT_TX_OVFL_MASK, /*!< Tx overflow flag. */ + kNETC_TxUnderflowFlag = NETC_ETH_LINK_PM0_IEVENT_TX_UNFL_MASK, /*!< Tx underflow flag. */ + kNETC_RxOverflowFlag = NETC_ETH_LINK_PM0_IEVENT_RX_OVFL_MASK, /*!< Rx overflow flag. */ + kNETC_MagicPacketFlag = NETC_ETH_LINK_PM0_IEVENT_MGI_MASK, /*!< Magic packet detection indication flag. */ + kNETC_TxClkStopFlag = NETC_ETH_LINK_PM0_IEVENT_TX_CSD_MASK, /*!< Tx clock stop detection flag. */ + kNETC_RxClkStopFlag = NETC_ETH_LINK_PM0_IEVENT_RX_CSD_MASK, /*!< Rx clock stop detection flag. */ + kNETC_SpeedDuplexChangeFlag = NETC_ETH_LINK_PM0_IEVENT_SPD_DUP_MASK, /*!< Speed/Duplex Change flag */ + kNETC_MacMergeSMDErrFlag = + NETC_ETH_LINK_PM0_IEVENT_MRG_SERR_MASK, /*!< MAC merge frame SMD error received event flag */ + kNETC_MacMergeAssemblyErrFlag = + NETC_ETH_LINK_PM0_IEVENT_MRG_AERR_MASK, /*!< MAC merge frame assembly error event flag */ } netc_port_intr_flags_t; /*! @brief Defines the port MAC frame loopback mode. */ typedef enum _netc_port_loopback_mode_t { - kNETC_PortLpbWithExtTxClk, /*!< Port MAC frame loopback with external Tx clock. */ + kNETC_PortLpbWithExtTxClk, /*!< Port MAC frame loopback with external Tx clock. */ kNETC_PortLpbWithIntTxClk = 2U, /*!< Port MAC frame loopback with internal Tx clock. */ } netc_port_loopback_mode_t; @@ -246,13 +248,59 @@ static inline status_t NETC_PortGetTcMaxSDU(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, netc_port_tc_sdu_config_t *config) { - config->maxSduSized = (uint16_t)(base->TCT_NUM[tcIdx].PTCTMSDUR & NETC_PORT_PTCTMSDUR_MAXSDU_MASK) >> NETC_PORT_PTCTMSDUR_MAXSDU_SHIFT; - config->enTxMaxSduCheck = (bool)((base->TCT_NUM[tcIdx].PTCTMSDUR & NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_MASK) >> NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT); - config->sduType = (netc_tc_sdu_type_t)(uint32_t)((base->TCT_NUM[tcIdx].PTCTMSDUR & NETC_PORT_PTCTMSDUR_SDU_TYPE_MASK) >> NETC_PORT_PTCTMSDUR_SDU_TYPE_SHIFT); + config->maxSduSized = (uint16_t)(base->TCT_NUM[tcIdx].PTCTMSDUR & NETC_PORT_PTCTMSDUR_MAXSDU_MASK) >> + NETC_PORT_PTCTMSDUR_MAXSDU_SHIFT; + config->enTxMaxSduCheck = (bool)((base->TCT_NUM[tcIdx].PTCTMSDUR & NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_MASK) >> + NETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT); + config->sduType = + (netc_tc_sdu_type_t)(uint32_t)((base->TCT_NUM[tcIdx].PTCTMSDUR & NETC_PORT_PTCTMSDUR_SDU_TYPE_MASK) >> + NETC_PORT_PTCTMSDUR_SDU_TYPE_SHIFT); return kStatus_Success; } +/*! + * @brief Config Frame Preemption for specified Port Traffic Class + * + * @param base NETC PORT base peripheral address + * @param tcIdx traffic class index + * @param enable enable/disable feature on traffic class + */ +static inline void NETC_PortConfigTcPreemption(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, const bool enable) +{ + uint32_t temp = base->PFPCR; + + temp &= (~((uint32_t)1U << (uint8_t)tcIdx)); + temp |= ((uint32_t)enable << (uint8_t)tcIdx); + base->PFPCR = temp; +} + +/*! + * @brief Get Frame Preemption configuration for specified Port Traffic Class + * + * @param base NETC PORT base peripheral address + * @param tcIdx traffic class index + * @param enabled port tx traffic class enabled flag + */ +static inline void NETC_PortGetTcPreemption(NETC_PORT_Type *base, netc_hw_tc_idx_t tcIdx, bool *enabled) +{ + *enabled = (base->PFPCR & ((uint32_t)1U << (uint8_t)tcIdx)) ? true : false; +} + +/*! + * @brief Get the port time gating Scheduling configuration specifc for when + * used with Frame Preemption + * + * @param base NETC PORT base peripheral address + * @param config + */ +static inline void NETC_PortGetTGSFPConfig(NETC_PORT_Type *base, netc_port_tg_preemption_config *config) +{ + config->holdAdvance = (base->PTGSHAR & NETC_PORT_PTGSHAR_HOLDADVANCE_MASK) >> NETC_PORT_PTGSHAR_HOLDADVANCE_SHIFT; + config->releaseAdvance = + (base->PTGSRAR & NETC_PORT_PTGSRAR_RELEASEADVANCE_MASK) >> NETC_PORT_PTGSRAR_RELEASEADVANCE_SHIFT; +} + /*! @} */ // end of netc_hw_port_tx #if !(defined(__GNUC__) || defined(__ICCARM__)) #pragma endregion netc_hw_port_tx @@ -299,9 +347,9 @@ static inline void NETC_PortSetVlanClassify(NETC_PORT_Type *base, const netc_por static inline status_t NETC_PortSetQosClassify(NETC_PORT_Type *base, const netc_port_qos_classify_config_t *config) { #if defined(FSL_FEATURE_NETC_HAS_ERRATA_051649) && FSL_FEATURE_NETC_HAS_ERRATA_051649 - /* ERRATA051649: Only mapping profile instance 0 can be used. Mapping profile instance 1 cannot be used due the decoding of the selected - profile is not correct. Therefore, if any switch port is configured to use the second mapping profile (1), all switch ports will not - assign the default QoS correctly. */ + /* ERRATA051649: Only mapping profile instance 0 can be used. Mapping profile instance 1 cannot be used due the + decoding of the selected profile is not correct. Therefore, if any switch port is configured to use the second + mapping profile (1), all switch ports will not assign the default QoS correctly. */ if (config->vlanQosMap != 0U) { return kStatus_InvalidArgument; @@ -379,7 +427,10 @@ void NETC_ClearPortMacInterruptFlags(NETC_ETH_LINK_Type *base, netc_port_phy_mac * of constants that should be OR'd together to form the bit mask. * @param enable Enable/Disable interrupts. */ -void NETC_EnablePortMacInterrupts(NETC_ETH_LINK_Type *base, netc_port_phy_mac_type_t macType, uint32_t mask, bool enable); +void NETC_EnablePortMacInterrupts(NETC_ETH_LINK_Type *base, + netc_port_phy_mac_type_t macType, + uint32_t mask, + bool enable); /*! * @brief Enable/Disable Loopback for specified MAC @@ -435,6 +486,23 @@ status_t NETC_PortSetMaxFrameSize(NETC_ETH_LINK_Type *base, uint16_t size); */ status_t NETC_PortConfigEthMac(NETC_ETH_LINK_Type *base, const netc_port_ethmac_t *config); +/*! + * @brief Configure ethernet MAC for Frame preemption + * on specified PORT. + * + * @param base Ethernet MAC port peripheral base address. + * @param config The Ethernet MAC configuration. + * @return status_t + */ +static inline void NETC_PortConfigEthMacPreemption(NETC_ETH_LINK_Type *base, const netc_port_preemption_config *config) +{ + base->MAC_MERGE_MMCSR = (base->MAC_MERGE_MMCSR & NETC_ETH_LINK_MAC_MERGE_MMCSR_LINK_FAIL(1U)) | + NETC_ETH_LINK_MAC_MERGE_MMCSR_VT(config->mergeVerifyTime) | + NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS(!config->enMergeVerify) | + NETC_ETH_LINK_MAC_MERGE_MMCSR_ME(config->preemptMode) | + NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS(config->raf_size); +} + /*! * @brief Do software reset for Ethernet MAC. * @@ -463,9 +531,37 @@ static inline void NETC_PortSoftwareResetEthMac(NETC_ETH_LINK_Type *base) static inline void NETC_PortGetPhyMacPreemptionStatus(NETC_ETH_LINK_Type *base, netc_port_phy_mac_preemption_status_t *status) { - status->verifyStatus = (netc_port_preemption_verify_status_t)(uint32_t)( - (base->MAC_MERGE_MMCSR & NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_MASK) >> NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_SHIFT); - status->mergeActive = ((base->MAC_MERGE_MMCSR & NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS_MASK) != 0U) ? true : false; + status->verifyStatus = (netc_port_preemption_verify_status_t)(uint32_t)((base->MAC_MERGE_MMCSR & + NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_MASK) >> + NETC_ETH_LINK_MAC_MERGE_MMCSR_VSTS_SHIFT); + status->mergeActive = ((base->MAC_MERGE_MMCSR & NETC_ETH_LINK_MAC_MERGE_MMCSR_TXSTS_MASK) != 0U) ? true : false; +} + +/*! + * @brief Get Ethernet MAC preemption control parameters. + * + * @param base PORT MAC peripheral base address. + * @param config Pointer to the NETC port preemption configuration. + */ +static inline void NETC_PortGetPhyMacPreemptionControl(NETC_ETH_LINK_Type *base, netc_port_preemption_config *config) +{ + uint32_t mmcsr; + + mmcsr = base->MAC_MERGE_MMCSR; + config->enMergeVerify = + ((mmcsr & NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS_MASK) >> NETC_ETH_LINK_MAC_MERGE_MMCSR_VDIS_SHIFT) ? false : true; + + config->mergeVerifyTime = + (uint8_t)((mmcsr & NETC_ETH_LINK_MAC_MERGE_MMCSR_VT_MASK) >> NETC_ETH_LINK_MAC_MERGE_MMCSR_VT_SHIFT); + + config->preemptMode = (netc_hw_preemption_mode_t)((mmcsr & NETC_ETH_LINK_MAC_MERGE_MMCSR_ME_MASK) >> + NETC_ETH_LINK_MAC_MERGE_MMCSR_ME_SHIFT); + + config->raf_size = (netc_hw_raf_size_t)((mmcsr & NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS_MASK) >> + NETC_ETH_LINK_MAC_MERGE_MMCSR_RAFS_SHIFT); + + config->PreemptionActive = + ((mmcsr & NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA_MASK) >> NETC_ETH_LINK_MAC_MERGE_MMCSR_LPA_SHIFT) ? true : false; } /*! diff --git a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_si.h b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_si.h index 7f9c38ce4c..cc591c948c 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_si.h +++ b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw_si.h @@ -1,5 +1,5 @@ /* - * Copyright 2021-2022 NXP + * Copyright 2021-2022, 2024-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,15 +25,26 @@ /*! @name Control and status bit masks of the transmit buffer descriptor. */ /*! @{ */ /*! @brief Defines for read format. */ -#define NETC_SI_TXDESCRIP_RD_TXSTART(n) ((uint32_t)(n)&0x1ffffffUL) -#define NETC_SI_TXDESCRIP_RD_DR(n) (((uint32_t)(n)&0x3U) << 10U) -#define NETC_SI_TXDESCRIP_RD_IPV(n) (((uint32_t)(n)&0x7U) << 12U) -#define NETC_SI_TXDESCRIP_RD_PORT(n) (((uint32_t)(n)&0x1fU) << 16U) -#define NETC_SI_TXDESCRIP_RD_TSR_MASK (1UL << 22U) -#define NETC_SI_TXDESCRIP_RD_SMSO_MASK (1UL << 23U) -#define NETC_SI_TXDESCRIP_RD_FLQ(n) (((uint32_t)(n)&0x03U) << 24U) +#define NETC_SI_TXDESCRIP_RD_FL(n) (((uint32_t)(n) & 0x03U) << 27U) #define NETC_SI_TXDESCRIP_RD_TSE_MASK (1UL << 25U) -#define NETC_SI_TXDESCRIP_RD_FL(n) (((uint32_t)(n)&0x03U) << 27U) +#define NETC_SI_TXDESCRIP_RD_TXSTART(n) ((uint32_t)(n) & 0x1fffffUL) +#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) +#define NETC_SI_TXDESCRIP_RD_DR(n) (((uint32_t)(n) & 0x3U) << 10U) +#define NETC_SI_TXDESCRIP_RD_IPV(n) (((uint32_t)(n) & 0x7U) << 12U) +#define NETC_SI_TXDESCRIP_RD_PORT(n) (((uint32_t)(n) & 0x1FU) << 16U) +#define NETC_SI_TXDESCRIP_RD_TSR_MASK (1UL << 22U) +#define NETC_SI_TXDESCRIP_RD_SMSO_MASK (1UL << 23U) +#define NETC_SI_TXDESCRIP_RD_FLQ(n) (((uint32_t)(n) & 0x3U) << 24U) +#else +#define NETC_SI_TXDESCRIP_RD_L3START(n) ((uint32_t)(n) & 0x7FU) +#define NETC_SI_TXDESCRIP_RD_IPCS(n) (((uint32_t)(n) & 0x1U) << 7U) +#define NETC_SI_TXDESCRIP_RD_L3HDRSIZE(n) (((uint32_t)(n) & 0x7FU) << 8U) +#define NETC_SI_TXDESCRIP_RD_L3T(n) (((uint32_t)(n) & 0x1U) << 15U) +#define NETC_SI_TXDESCRIP_RD_L4T(n) (((uint32_t)(n) & 0x3U) << 21U) +#define NETC_SI_TXDESCRIP_RD_L4CS(n) (((uint32_t)(n) & 0x1U) << 24U) +#define NETC_SI_TXDESCRIP_RD_LSO(n) (((uint32_t)(n) & 0x1U) << 25U) +#define NETC_SI_TXDESCRIP_RD_LSO_MASK (((uint32_t)0x1U) << 25U) +#endif /*! @} */ /*! diff --git a/mcux/mcux-sdk-ng/drivers/netc/socs/imx943/fsl_netc_soc.c b/mcux/mcux-sdk-ng/drivers/netc/socs/imx943/fsl_netc_soc.c index e37a0f91d2..714b3725d3 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/socs/imx943/fsl_netc_soc.c +++ b/mcux/mcux-sdk-ng/drivers/netc/socs/imx943/fsl_netc_soc.c @@ -1,10 +1,11 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_netc_soc.h" +#include "fsl_netc_phy_wrapper.h" /*! @brief Pointers to enetc si bases for each instance. */ static ENETC_SI_Type *const s_enetcSiBases[] = ENETC_SI_BASE_PTRS; @@ -32,24 +33,520 @@ void NETC_SocGetBaseResource(netc_enetc_hw_t *hw, netc_hw_si_idx_t si) hw->global = (ENETC_GLOBAL_Type *)((uintptr_t)hw->base + 0x10000U); if (siNum == 0U) { - hw->func.pf = s_netcBases[1 + siIdx]; + hw->func.pf = s_netcBases[1 + siIdx]; hw->msixTable = (netc_msix_entry_t *)((uintptr_t)hw->si + 0x30000U); } else { - hw->func.vf = s_netcVfBases[siIdx - 3]; + hw->func.vf = s_netcVfBases[siIdx - 3]; hw->msixTable = (netc_msix_entry_t *)((uintptr_t)hw->si + 0x60000U); } } uint32_t NETC_SocGetFuncInstance(netc_hw_eth_port_idx_t port) { - uint32_t instance = (uint32_t)port + 1U; + if (port >= kNETC_SWITCH0EthPort0) + { + return 5U; + } - return instance; + return ((uint32_t)port + 1U); } -status_t NETC_SocPreInitVsi(netc_enetc_hw_t *hw, netc_hw_si_idx_t si) +static uint32_t NETC_PHYRead(netc_mdio_handle_t *handle, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr) { + uint16_t val = 0U; + status_t status; + + status = NETC_MDIOC45Read(handle, portAddr, devAddr, regAddr, &val); + if (status != kStatus_Success) + { + assert(false); + } + + return val; +} + +static void NETC_PHYWrite(netc_mdio_handle_t *handle, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t val) +{ + status_t status; + + status = NETC_MDIOC45Write(handle, portAddr, devAddr, regAddr, val); + if (status != kStatus_Success) + { + assert(false); + } +} + +status_t NETC_PHYInit(netc_mdio_handle_t *handle, phy_mode_t mode) +{ + static int already_done = 0; + static uint32_t ref_clk_init = 0; + uint32_t value; + uint32_t sel_mplla = 0; + uint32_t sel_mpllb = 0; + int portId = 0; + + if (handle->mdio.port == kNETC_SWITCH0EthPort0) + { + portId = 0; + BLK_CTRL_NETCMIX->MISC_SOC_CONTROL &= 0xFFFFFFFD; + } + + if (handle->mdio.port == kNETC_SWITCH0EthPort1) + { + portId = 1; + BLK_CTRL_NETCMIX->MISC_SOC_CONTROL |= 0x2; + } + + NETC_PHYWrite(handle, 0x10, 0x1f, 0x200 >> 1, 0x80); + NETC_PHYWrite(handle, 0x10, 0x1f, 0x204 >> 1, 0x80); + NETC_PHYWrite(handle, 0x10, 0x1f, 0x208 >> 1, 0x80); + NETC_PHYWrite(handle, 0x10, 0x1f, 0x20c >> 1, 0x80); + + if (already_done == 0) + { + value = NETC_PHYRead(handle, 0x10, 0x01, 0x0056); + value = ((value & 0xF0FF) | (portId << 8)); + NETC_PHYWrite(handle, 0x10, 0x01, 0x0056, value); + } + + value = NETC_PHYRead(handle, 0x10, 0x0, 0x124 >> 1); + value = (value | 0x0100 | 0x4000); + NETC_PHYWrite(handle, 0x10, 0x0, 0x124 >> 1, value); + + SDK_DelayAtLeastUs(4000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + value = NETC_PHYRead(handle, 0x0, 0x1F, 0x809B); + while ((value & 0x00000001) == 0) + { + value = NETC_PHYRead(handle, 0x0, 0x1F, 0x809B); + } + if (already_done == 0) + { + NETC_PHYWrite(handle, 0x10, 0x0, 0x114 >> 1, (0x101 | sel_mpllb << 7 | sel_mplla << 6)); + } + + value = NETC_PHYRead(handle, 0x0, 0x5E, 0x0); + while ((value & 0x00008000) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x0); + } + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x0); + value = ((value & 0xEFFF) | 0x0000); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x0, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8030); + value = (value | 0x0100); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8030, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8051); + value = (value | 0x0010); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8051, value); + + SDK_DelayAtLeastUs(1000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8030); + value = (value & 0xFEFF); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8030, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8051); + value = (value & 0xFFEF); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8051, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8040); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8040); + } + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8035); + value = ((value & 0xFFFC) | 0x0003); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8035, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8070); + value = ((value & 0xFFFE)); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8070, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8030); + value = (value & 0xEFFF); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8030, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8060); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8060); + } + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8050); + value = ((value & 0xFEFF)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8050, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8055); + value = ((value & 0xFFFC) | 0x0001); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8055, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8055); + value = ((value & 0xFFFC) | 0x0003); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8055, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + value = ((value & 0xFFFE) | 0x0001); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8032, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + value = ((value & 0xFFFE) | 0x0001); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8052, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + } + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + } + + SDK_DelayAtLeastUs(1000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + value = ((value & 0xFFFE)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8032, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + value = ((value & 0xFFFE)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8052, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8040); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8040); + } + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8060); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8060); + } + + if (already_done == 0) + { + if (ref_clk_init == 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8091); + value = ((value & 0xFF03) | 0x00F0); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8091, value); + ref_clk_init++; + } + + SDK_DelayAtLeastUs(6000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8073); + value = ((value & 0xE000) | 0x028A); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8073, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8072); + value = ((value & 0x0)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8072, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x807A); + value = ((value & 0x0)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x807A, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8079); + value = ((value & 0x0)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8079, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x807A); + value = ((value & 0x0)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x807A, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8072); + value = ((value & 0x0)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8072, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8071); + value = ((value & 0xFF00) | 0x0028); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8071, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8077); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8077, 0xA017); + } + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8090); + value = ((value & 0xE0FF) | 0x1100); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8090, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x809C); + value = ((value & 0xFF00) | 0x0001); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x809C, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8096); + value = ((value & 0xFF80) | 0x0022); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8096, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8092); + value = ((value & 0xE000) | 0x0550); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8092, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8065); + value = ((value & 0xFFE0) | 0x0012); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8065, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8070); + value = ((value & 0xFFEF)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8070, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x803E); + value = ((value & 0xFF00) | 0x0000); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x803E, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8034); + value = ((value & 0xFFF8) | 0x0002); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8034, value); + + SDK_DelayAtLeastUs(1000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8034); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + value = ((value & 0xFCFF) | 0x0100); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8032, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8031); + value = ((value & 0xF8FF) | 0x0700); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8031, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8031); + value = ((value & 0xFFEF) | 0x0010); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8031, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8033); + value = ((value & 0xFFF0) | 0x000F); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8033, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8036); + value = ((value & 0xFFC0)); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8036, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8037); + value = ((value & 0xFFC0) | 0x0020); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8037, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8036); + value = ((value & 0xC0FF) | 0x2000); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8036, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8054); + value = ((value & 0xFFFC) | 0x0002); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8054, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8058); + value = ((value & 0xFF80) | 0x0010); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8058, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8053); + value = ((value & 0xFFF8) | 0x0002); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8053, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8064); + value = ((value & 0xFFEE) | 0x0010); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8064, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8069); + value = ((value & 0xFF00) | 0x0017); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8069, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + value = ((value & 0xFCFF) | 0x0100); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8052, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8051); + value = ((value & 0xEFFF)); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8051, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8056); + value = ((value & 0xFFEF) | 0x0000); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8056, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8053); + value = ((value & 0xEFFF) | 0x0000); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8053, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8068); + value = ((value & 0xFEFF) | 0x0100); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8068, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8057); + value = ((value & 0xFFF8) | 0x0000); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8057, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8058); + value = ((value & 0x88FF) | 0x4400); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8058, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x805E); + value = ((value & 0xFF00) | 0x0000); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x805E, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8064); + value = ((value & 0xFCFF) | 0x0200); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8064, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8051); + value = ((value & 0xFEFF) | 0x0100); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8051, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x806B); + value = ((value & 0xF0FF) | 0x0000); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x806B, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x805D); + value = ((value & 0xFFCE) | 0x0000); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x805D, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8000); + value = ((value & 0xFFFB) | 0x0004); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8000, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x805C); + value = ((value & 0xFFFE) | 0x0000); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x805C, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8000); + value = ((value & 0x7FFF) | 0x8000); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8000, value); + + value = NETC_PHYRead(handle, 0x0, 0x1F, 0x809B); + while ((value & 0x00000001) == 0) + { + value = NETC_PHYRead(handle, 0x0, 0x1F, 0x809B); + } + + SDK_DelayAtLeastUs(1000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + if (already_done == 0) + { + NETC_PHYWrite(handle, 0x10, 0x0, 0x114 >> 1, (0x101 | sel_mpllb << 7 | sel_mplla << 6)); + } + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8000); + while ((value & 0x00008000) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8000); + } + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8031); + value = ((value & 0xEFFF) | 0x1000); + NETC_PHYWrite(handle, 0x0, 0x1F, 0x8031, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8005); + value = ((value & 0xFFAF)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8005, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8005); + value = ((value & 0xFEFF) | 0x0100); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8005, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8035); + value = ((value & 0xFFFC) | 0x0002); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8035, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8070); + value = ((value & 0xFFFE) | 0x0001); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8070, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + value = ((value & 0xFFFE) | 0x0001); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8032, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + value = ((value & 0xFFFE) | 0x0001); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8052, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + } + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + } + + SDK_DelayAtLeastUs(1000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8035); + value = ((value & 0xFFFC) | 0x0000); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8035, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8035); + value = ((value & 0xFEFF)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8035, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8055); + value = ((value & 0xFEFC) | 0x0000); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8055, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8030); + value = ((value & 0xEFFF) | 0x1000); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8030, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8050); + value = ((value & 0xFEFF) | 0x0100); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8050, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + value = ((value & 0xFFFE) | 0x0001); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8032, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + value = ((value & 0xFFFE) | 0x0001); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8052, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + } + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + } + + SDK_DelayAtLeastUs(1000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8032); + value = ((value & 0xFFFE)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8032, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8052); + value = ((value & 0xFFFE)); + NETC_PHYWrite(handle, 0x0, 0x5F, 0x8052, value); + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8040); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8040); + } + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8060); + while ((value & 0x00000001) != 0) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x8060); + } + + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x1); + while ((value & 0x00000004) != 4) + { + value = NETC_PHYRead(handle, 0x0, 0x5F, 0x1); + } + + already_done = 1; + return kStatus_Success; } diff --git a/mcux/mcux-sdk-ng/drivers/netc/socs/imx943/fsl_netc_soc.h b/mcux/mcux-sdk-ng/drivers/netc/socs/imx943/fsl_netc_soc.h index a5438afbde..fdc49c6aae 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/socs/imx943/fsl_netc_soc.h +++ b/mcux/mcux-sdk-ng/drivers/netc/socs/imx943/fsl_netc_soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2024 NXP + * Copyright 2024-2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +16,23 @@ #define NETC_SOC_SWT_PORT_NUM (4U) /*! @brief The Switch function register base address offset.(SW0_PCI_HDR_TYPE0) */ -#define NETC_SOC_SWT_PCIE_FUNC_OFFSET (5U) +#define NETC_SOC_SWT_PCIE_FUNC_OFFSET (5U) +#define NETC_SOC_SWT_MSI_FUNC_OFFSET (0U) + +/*! @name NETC register map. */ +/*@{*/ +#define NETC_SWT_COMMON_BASE_OFFSET (0x1000U) /*!< The ENETC common register base address offset. */ +#define NETC_SWT_GLOBAL_BASE_OFFSET (0x70000U) /*!< The Switch global register base address offset. */ +/*@}*/ + +/* + * port3 port2 port1 port0 + * 0x08 = 0b 0000 1 0 0 0 + * It means that input frame will forward to switch port3 + */ +#ifndef NETC_SOC_INPUT_FRM_SWT_PORT_BITMAP +#define NETC_SOC_INPUT_FRM_SWT_PORT_BITMAP (0x08) +#endif /*! @brief Station interface index enumerator */ typedef enum _netc_hw_si_idx @@ -66,12 +82,4 @@ void NETC_SocGetBaseResource(netc_enetc_hw_t *hw, netc_hw_si_idx_t si); */ uint32_t NETC_SocGetFuncInstance(netc_hw_eth_port_idx_t port); -/*! - * @brief Preinit VSIs - * - * @param hw The enetc hw handle. - * @param si The SI object. - * @return status_t - */ -status_t NETC_SocPreInitVsi(netc_enetc_hw_t *hw, netc_hw_si_idx_t si); #endif /* _FSL_NETC_SOC_H_ */ diff --git a/mcux/mcux-sdk-ng/drivers/netc/socs/imx95/fsl_netc_soc.c b/mcux/mcux-sdk-ng/drivers/netc/socs/imx95/fsl_netc_soc.c index 1f05253fe9..e0596cd4a5 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/socs/imx95/fsl_netc_soc.c +++ b/mcux/mcux-sdk-ng/drivers/netc/socs/imx95/fsl_netc_soc.c @@ -1,10 +1,29 @@ /* - * Copyright 2023 NXP + * Copyright 2023, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_netc_soc.h" +#include "fsl_netc_phy_wrapper.h" + +#define NETC_PHY_WRITE_BITS(h, p, r, m, v) \ + { \ + status = NETC_PHYWriteRegBits(h, p, r, m, v); \ + if (status != kStatus_Success) \ + { \ + return status; \ + } \ + } + +#define NETC_PHY_READ(h, p, r, v) \ + { \ + status = NETC_PHYReadReg(h, p, r, v); \ + if (status != kStatus_Success) \ + { \ + return status; \ + } \ + } /*! @brief Pointers to enetc si bases for each instance. */ static ENETC_SI_Type *const s_enetcSiBases[] = ENETC_SI_BASE_PTRS; @@ -32,12 +51,12 @@ void NETC_SocGetBaseResource(netc_enetc_hw_t *hw, netc_hw_si_idx_t si) hw->global = (ENETC_GLOBAL_Type *)((uintptr_t)hw->base + 0x10000U); if (siNum == 0U) { - hw->func.pf = s_netcBases[1U + siIdx]; + hw->func.pf = s_netcBases[1U + siIdx]; hw->msixTable = (netc_msix_entry_t *)((uintptr_t)hw->si + 0x30000U); } else { - hw->func.vf = s_netcVfBases[siIdx - 3U]; + hw->func.vf = s_netcVfBases[siIdx - 3U]; hw->msixTable = (netc_msix_entry_t *)((uintptr_t)hw->si + 0x60000U); } } @@ -49,87 +68,523 @@ uint32_t NETC_SocGetFuncInstance(netc_hw_eth_port_idx_t port) return instance; } -status_t NETC_SocPreInitVsi(netc_enetc_hw_t *hw, netc_hw_si_idx_t si) +status_t NETC_PHYInit(netc_mdio_handle_t *handle, phy_mode_t mode) { - uint8_t macAddr0[] = { 0x00, 0x00, 0xfa, 0xfa, 0xdd, 0xa0 }; - uint8_t macAddr1[] = { 0x00, 0x00, 0xfa, 0xfa, 0xdd, 0xa1 }; - netc_hw_enetc_si_config_t vsi0Config = { - .txRingUse = 3U, .rxRingUse = 3U, .vlanCtrl = (uint32_t)kNETC_ENETC_StanCVlan | (uint32_t)kNETC_ENETC_StanSVlan}; - netc_hw_enetc_si_config_t vsi1Config = { - .txRingUse = 4U, .rxRingUse = 4U, .vlanCtrl = (uint32_t)kNETC_ENETC_StanCVlan | (uint32_t)kNETC_ENETC_StanSVlan}; - netc_si_l2vf_config_t vlanConfig = { - .acceptUntagged = true, .enPromis = true, .useOuterVlanTag = true}; - uint32_t vsi0MsixNum = 4U; - uint32_t vsi1MsixNum = 5U; - uint8_t vsi0Num; - uint8_t vsi1Num; - status_t result; - - switch (si) - { - case kNETC_ENETC0PSI0: - vsi0Num = getSiNum(kNETC_ENETC0VSI0); - vsi1Num = getSiNum(kNETC_ENETC0VSI1); - break; - case kNETC_ENETC1PSI0: - vsi0Num = getSiNum(kNETC_ENETC1VSI0); - vsi1Num = getSiNum(kNETC_ENETC1VSI1); - break; - case kNETC_ENETC2PSI0: - vsi0Num = getSiNum(kNETC_ENETC2VSI0); - vsi1Num = getSiNum(kNETC_ENETC2VSI1); - break; - default: - assert(false); - break; - } +#if !(defined(FSL_FEATURE_NETC_HAS_NO_XGMII) && FSL_FEATURE_NETC_HAS_NO_XGMII) + uint16_t regValue; + status_t status; - /* RSS key init with generated random values */ - hw->base->PRSSKR0 = 0x995770eaU; - hw->base->PRSSKR1 = 0x7e8cbbe3U; - hw->base->PRSSKR2 = 0x9ac8285bU; - hw->base->PRSSKR3 = 0xce20c189U; - hw->base->PRSSKR4 = 0xb7ece3ebU; - hw->base->PRSSKR5 = 0xf8bc2513U; - hw->base->PRSSKR6 = 0x62613353U; - hw->base->PRSSKR7 = 0x4c84ae76U; - hw->base->PRSSKR8 = 0x72c890f1U; - hw->base->PRSSKR9 = 0xd7a8144bU; - - /* Preinit vsi0 for mac address, BDR num, and MSIX interrupt num */ - NETC_EnetcSetSIMacAddr(hw->base, vsi0Num, macAddr0); - - result = NETC_EnetcSetMsixEntryNum(hw->base, vsi0Num, vsi0MsixNum); - if (result != kStatus_Success) + if ((mode == kNETC_XGMII10G) || (mode == kNETC_XGMII10GAuto)) { - return result; - } + NETC_PHY_WRITE_BITS(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_PHY, + ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK_MASK, + ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_PHY_LOCK(0x1U)); + NETC_PHY_WRITE_BITS(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_MPLLA, + ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK_MASK, + ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLA_LOCK(0x1U)); + NETC_PHY_WRITE_BITS(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_MPLLB, + ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK_MASK, + ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_MPLLB_LOCK(0x1U)); + NETC_PHY_WRITE_BITS(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_RAM, + ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK_MASK, + ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_RAM_LOCK(0x1U)); + NETC_PHY_WRITE_BITS(handle, false, &ENET_PHY_MAC_ADAPTER->MAC_ADAPTER_LOCK_ROM, + ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK_MASK, + ENET_PHY_MAC_ADAPTER_MAC_ADAPTER_LOCK_ROM_LOCK(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_SRAM, ®Value); + regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN_MASK; + } while (regValue == 0x0U); + NETC_PHY_WRITE_BITS(handle, false, &ENET_PHY_CTRL_EX->GLOBAL_CTRL_EX_0, + ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS_MASK, + ENET_PHY_CTRL_EX_GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_XS_PCS_MMD->SR_XS_PCS_CTRL1, ®Value); + regValue &= ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL1_RST_MASK; + } while (regValue != 0x0U); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, + ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE_MASK, + ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x1U)); + SDK_DelayAtLeastUs(1, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE(0x3U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x3U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, ®Value); + regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK; + } while (regValue != 0x0U); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value); + regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK; + } while (regValue != 0x0U); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RANGE_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_RANGE(0x6U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_DIV2_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_CLK_DIV2(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV2_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_REF_CLK_CTRL_REF_MPLLA_DIV2(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_TX_CLK_DIV(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_CLK_EN_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_CLK_EN(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_MULT_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV_MULT(0x5U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_EN_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_EN(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL5, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL4, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL5, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_SPD_EN_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL5_MPLLA_SSC_SPD_EN(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_FRACN_CTRL_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL1_MPLLA_FRACN_CTRL(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER(0x21U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_LVL_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_LVL(0x5U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL3, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX_VREF_CTRL_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_CTRL0_RX_VREF_CTRL(0x11U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_MISC_CTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_SUP_MISC_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_MISC_CTRL2_SUP_MISC(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0(0x29U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0(0x549U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0_RX0_CDR_PPM_MAX_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_PPM_CTRL0_RX0_CDR_PPM_MAX(0x12U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0_TX0_MISC_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_TX_MISC_CTRL0_TX0_MISC(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLLB_SEL_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLLB_SEL_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH(0x3U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL_TX0_IBOOST_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_BOOST_CTRL_TX0_IBOOST(0xFU)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_PRE_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_PRE(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1_TX_EQ_POST_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL1_TX_EQ_POST(0x20U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_MAIN_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_EQ_CTRL0_TX_EQ_MAIN(0x20U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_POLE_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_POLE_0(0x2U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0(0x10U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL3, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_TRSHLD_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_TRSHLD_0(0x7U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC(0x12U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH(0x3U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL_CDR_SSC_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_CDR_CTRL_CDR_SSC_EN_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL3, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_LFPS_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL3_LOS_LFPS_EN_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_GENCTRL4, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL_RX0_EQ_ATT_LVL_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_ATTN_CTRL_RX0_EQ_ATT_LVL(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA1_GAIN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA1_GAIN_0(0x5U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA2_GAIN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_VGA2_GAIN_0(0x5U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0_DFE_TAP1_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_DFE_TAP_CTRL0_DFE_TAP1_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_TERM_ACDC_0_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_TERM_ACDC_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_SEL_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX_ADPT_SEL_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE(0x3U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_XS_PCS_MMD->SR_XS_PCS_CTRL2, + ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL_MASK, + ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USXG_EN_MASK, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USXG_EN(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_KR_CTRL, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_MODE_MASK, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_KR_CTRL_USXG_MODE(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_XS_PCS_MMD->SR_XS_PCS_CTRL2, + ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL_MASK, + ENET_PHY_XS_PCS_MMD_SR_XS_PCS_CTRL2_PCS_TYPE_SEL(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL0_MPLLA_MULTIPLIER(0x21U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_MPLLA_CTRL3, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_VCO_CAL_LD0_VCO_LD_VAL_0(0x549U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_VCO_CAL_REF0_VCO_REF_LD_0(0x29U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_ADAPT_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_CONT_ADAPT_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_RATE_CTRL_TX0_RATE(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_RATE_CTRL_RX0_RATE(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX0_WIDTH(0x3U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX0_WIDTH(0x3U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_VBOOST_EN_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL0_CTLE_BOOST_0(0x10U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_STEP_CTRL_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_MISC_CTRL0_RX0_MISC(0x12U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_GENCTRL4, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_GENCTRL4_RX_DFE_BYP_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_RX_CDR_CTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_RX_CDR_CTRL1_VCO_FRQBAND_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_IQ_CTRL0_RX0_DELTA_IQ(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_16G_25G_RX_EQ_CTRL5_RX0_ADPT_MODE(0x3U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST_MASK, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_SRAM, ®Value); + regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_INIT_DN_MASK; + } while (regValue == 0x0U); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_SRAM, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_EXT_LD_DN_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_SRAM_EXT_LD_DN(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, ®Value); + regValue &= ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_VR_RST_MASK; + } while (regValue != 0x0U); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value); + regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK; + } while (regValue != 0x0U); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL1_TX_CLK_RDY_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DEBUG_CTRL, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_LOS_DET_MASK, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_SUPRESS_LOS_DET(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DEBUG_CTRL, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_DT_EN_CTL_MASK, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_RX_DT_EN_CTL(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_RX_LSTS, ®Value); + regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_RX_LSTS_RX_VALID_0_MASK; + } while (regValue == 0x0U); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MISC_STS, ®Value); + regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MISC_STS_RX_ADPT_ACK_MASK; + } while (regValue == 0x0U); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_EQ_CTRL4_RX_AD_REQ(0x0U)); - result = NETC_EnetcConfigureSI(hw->base, vsi0Num, &vsi0Config); - if (result != kStatus_Success) - { - return result; - } + if (mode == kNETC_XGMII10GAuto) + { + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_CTRL, + ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_AN_INTR_EN_MASK, + ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_MII_AN_INTR_EN(0x1U)); + } - NETC_EnetcEnableSI(hw->base, vsi0Num, true); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_CTRL, + ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_TX_CONFIG_MASK, + ENET_PHY_VS_MII_MMD_VR_MII_AN_CTRL_TX_CONFIG(0x0U)); - /* Preinit vsi1 for mac address, BDR num, and MSIX interrupt num */ - NETC_EnetcSetSIMacAddr(hw->base, vsi1Num, macAddr1); + if (mode == kNETC_XGMII10GAuto) + { + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_LINK_TIMER_CTRL, + ENET_PHY_VS_MII_MMD_VR_MII_LINK_TIMER_CTRL_CL37_LINK_TIME_MASK, + ENET_PHY_VS_MII_MMD_VR_MII_LINK_TIMER_CTRL_CL37_LINK_TIME(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_DIG_CTRL1, + ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_MASK, + ENET_PHY_VS_MII_MMD_VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE(0x1U)); + } - result = NETC_EnetcSetMsixEntryNum(hw->base, vsi1Num, vsi1MsixNum); - if (result != kStatus_Success) - { - return result; - } + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS6_MASK, + ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS6(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS13_MASK, + ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS13(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS5_MASK, + ENET_PHY_VS_MII_MMD_SR_MII_CTRL_SS5(0x0U)); + + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DEBUG_CTRL, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_TX_PMBL_CTL_MASK, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DEBUG_CTRL_TX_PMBL_CTL(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE(0x2U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, ®Value); + regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK; + } while (regValue != 0x0U); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value); + regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK; + } while (regValue != 0x0U); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX0_PSTATE(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_RST_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_TX_POWER_STATE_CTRL, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX_DISABLE_0_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_TX_POWER_STATE_CTRL_TX_DISABLE_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_MPLL_CMN_CTRL_MPLL_EN_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_GENCTRL1, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_GENCTRL1_RX_RST_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX_DISABLE_0(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->MP_12G_16G_25G_RX_POWER_STATE_CTRL, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK, + ENET_PHY_PMA_MMD_MP_12G_16G_25G_RX_POWER_STATE_CTRL_RX0_PSTATE(0x0U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_TX_GENCTRL0_TX_DT_EN_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_25G_RX_GENCTRL0_RX_DT_EN_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0(0x1U)); + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK, + ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_TX_GENCTRL2, ®Value); + regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_TX_GENCTRL2_TX_REQ_0_MASK; + } while (regValue != 0x0U); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_PMA_MMD->VR_XS_PMA_MP_12G_16G_RX_GENCTRL2, ®Value); + regValue &= ENET_PHY_PMA_MMD_VR_XS_PMA_MP_12G_16G_RX_GENCTRL2_RX_REQ_0_MASK; + } while (regValue != 0x0U); + + if (mode == kNETC_XGMII10GAuto) + { + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_VS_MII_MMD->SR_MII_CTRL, + ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE_MASK, + ENET_PHY_VS_MII_MMD_SR_MII_CTRL_AN_ENABLE(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_INTR_STS, ®Value); + regValue &= ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_MASK; + } while (regValue == 0x0U); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_INTR_STS, ®Value); + regValue &= ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_USXG_AN_STS_MASK; + } while (regValue != ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_USXG_AN_STS(0x2FU)); - result = NETC_EnetcConfigureSI(hw->base, vsi1Num, &vsi1Config); - if (result != kStatus_Success) + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_VS_MII_MMD->VR_MII_AN_INTR_STS, + ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_MASK, + ENET_PHY_VS_MII_MMD_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR(0x0U)); + + NETC_PHY_WRITE_BITS(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST_MASK, + ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST(0x1U)); + do + { + NETC_PHY_READ(handle, true, &ENET_PHY_XS_PCS_MMD->VR_XS_PCS_DIG_CTRL1, ®Value); + regValue &= ENET_PHY_XS_PCS_MMD_VR_XS_PCS_DIG_CTRL1_USRA_RST_MASK; + } while (regValue != 0U); + } + } + else { - return result; + return kStatus_NETC_Unsupported; } - NETC_EnetcEnableSI(hw->base, vsi1Num, true); - - NETC_EnetcConfigureVlanFilter(hw->base, getSiNum(si), &vlanConfig); - return result; +#endif + return kStatus_Success; } diff --git a/mcux/mcux-sdk-ng/drivers/netc/socs/imx95/fsl_netc_soc.h b/mcux/mcux-sdk-ng/drivers/netc/socs/imx95/fsl_netc_soc.h index c728216ce0..3d3b97945b 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/socs/imx95/fsl_netc_soc.h +++ b/mcux/mcux-sdk-ng/drivers/netc/socs/imx95/fsl_netc_soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -31,9 +31,9 @@ typedef enum _netc_hw_si_idx /*! @brief Ethernet MAC port resource for the NETC module */ typedef enum _netc_hw_eth_port_idx { - kNETC_ENETC0EthPort = 0U, /*!< Ethernet MAC port for ENETC0 */ - kNETC_ENETC1EthPort = 1U, /*!< Ethernet MAC port for ENETC1 */ - kNETC_ENETC2EthPort = 2U, /*!< Ethernet MAC port for ENETC2 */ + kNETC_ENETC0EthPort = 0U, /*!< Ethernet MAC port for ENETC0 */ + kNETC_ENETC1EthPort = 1U, /*!< Ethernet MAC port for ENETC1 */ + kNETC_ENETC2EthPort = 2U, /*!< Ethernet MAC port for ENETC2 */ } netc_hw_eth_port_idx_t; /*! @@ -61,12 +61,4 @@ void NETC_SocGetBaseResource(netc_enetc_hw_t *hw, netc_hw_si_idx_t si); */ uint32_t NETC_SocGetFuncInstance(netc_hw_eth_port_idx_t port); -/*! - * @brief Preinit VSIs - * - * @param hw The enetc hw handle. - * @param si The SI object. - * @return status_t - */ -status_t NETC_SocPreInitVsi(netc_enetc_hw_t *hw, netc_hw_si_idx_t si); #endif /* _FSL_NETC_SOC_H_ */ diff --git a/mcux/mcux-sdk-ng/drivers/netc/socs/imxrt1180/fsl_netc_soc.c b/mcux/mcux-sdk-ng/drivers/netc/socs/imxrt1180/fsl_netc_soc.c index 2c188195cf..64b4795ffa 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/socs/imxrt1180/fsl_netc_soc.c +++ b/mcux/mcux-sdk-ng/drivers/netc/socs/imxrt1180/fsl_netc_soc.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,7 +16,7 @@ static NETC_ENETC_Type *const s_netcEnetcBases[] = NETC_ENETC_BASE_PTRS; status_t NETC_SocSetMiiMode(netc_soc_link_t link, netc_hw_mii_mode_t miiMode) { - status_t result = kStatus_Success; + status_t result = kStatus_Success; BLK_CTRL_WAKEUPMIX_Type *base = BLK_CTRL_WAKEUPMIX; uint8_t miiSel; @@ -112,7 +112,8 @@ status_t NETC_SocSetTimer(netc_timer_exttrig_index_t timerTrigger, netc_soc_time BLK_CTRL_WAKEUPMIX_Type *base = BLK_CTRL_WAKEUPMIX; base->NETC_PORT_MISC_CFG &= ~(BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG1_SEL_MASK << (uint32_t)timerTrigger); - base->NETC_PORT_MISC_CFG |= (BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG1_SEL(inputSel) << (uint32_t)timerTrigger); + base->NETC_PORT_MISC_CFG |= + (BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_TRIG1_SEL(inputSel) << (uint32_t)timerTrigger); return kStatus_Success; } @@ -123,11 +124,13 @@ status_t NETC_SocSetRmiiRefClk(netc_soc_link_t link, bool output) if (output) { - base->NETC_PORT_MISC_CFG |= ((uint32_t)BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK << (uint32_t)link); + base->NETC_PORT_MISC_CFG |= + ((uint32_t)BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK << (uint32_t)link); } else { - base->NETC_PORT_MISC_CFG &= ~((uint32_t)BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK << (uint32_t)link); + base->NETC_PORT_MISC_CFG &= + ~((uint32_t)BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK << (uint32_t)link); } return kStatus_Success; @@ -146,10 +149,10 @@ void NETC_SocGetBaseResource(netc_enetc_hw_t *hw, netc_hw_si_idx_t si) hw->global = (ENETC_GLOBAL_Type *)((uintptr_t)hw->base + NETC_ENETC_GLOBAL_BASE_OFFSET); if (siNum == 0U) { - hw->func.pf = s_netcBases[NETC_ENETC_PCIE_FUNC_OFFSET + instance]; - hw->si = (ENETC_SI_Type *)((uintptr_t)hw->base - 0x10000U); - hw->msixTable = - (netc_msix_entry_t *)((uint32_t)FSL_FEATURE_NETC_MSIX_TABLE_BASE + NETC_MSIX_TABLE_OFFSET * (3U + (uint32_t)siIdx)); + hw->func.pf = s_netcBases[NETC_ENETC_PCIE_FUNC_OFFSET + instance]; + hw->si = (ENETC_SI_Type *)((uintptr_t)hw->base - 0x10000U); + hw->msixTable = (netc_msix_entry_t *)((uint32_t)FSL_FEATURE_NETC_MSIX_TABLE_BASE + + NETC_MSIX_TABLE_OFFSET * (3U + (uint32_t)siIdx)); } else { @@ -203,8 +206,3 @@ status_t NETC_SocSetLinkAddr(netc_soc_link_t link, uint8_t phyAddr) return result; } - -status_t NETC_SocPreInitVsi(netc_enetc_hw_t *hw, netc_hw_si_idx_t si) -{ - return kStatus_Success; -} diff --git a/mcux/mcux-sdk-ng/drivers/netc/socs/imxrt1180/fsl_netc_soc.h b/mcux/mcux-sdk-ng/drivers/netc/socs/imxrt1180/fsl_netc_soc.h index 222b983926..6a4c70f9ed 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/socs/imxrt1180/fsl_netc_soc.h +++ b/mcux/mcux-sdk-ng/drivers/netc/socs/imxrt1180/fsl_netc_soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023, 2025 NXP * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,13 +20,25 @@ #define NETC_ENETC_PCIE_FUNC_OFFSET (3U) /*!< The ENETC PCIE function index. */ #define NETC_ENETC_PORT_GROUP_BASE_OFFSET (0x4000U) /*!< The ENETC port group register base address offset. */ #define NETC_ENETC_GLOBAL_BASE_OFFSET (0x10000U) /*!< The ENETC global register base address offset. */ +#define NETC_SWT_COMMON_BASE_OFFSET (0x0U) /*!< The ENETC common register base address offset. */ +#define NETC_SWT_GLOBAL_BASE_OFFSET (0x80000U) /*!< The Switch global register base address offset. */ /*@}*/ /*! @brief Switch port numbers(Port0 ~ 4 in Switch Core). */ #define NETC_SOC_SWT_PORT_NUM (5U) /*! @brief The Switch function register base address offset.(NETC_F1_PCI_HDR_TYPE0) */ -#define NETC_SOC_SWT_PCIE_FUNC_OFFSET (2U) +#define NETC_SOC_SWT_PCIE_FUNC_OFFSET (2U) +#define NETC_SOC_SWT_MSI_FUNC_OFFSET (2U) + +/* + * port4 port3 port2 port1 port0 + * 0x10 = 0b 000 1 0 0 0 0 + * It means that input frame will forward to switch port4 + */ +#ifndef NETC_SOC_INPUT_FRM_SWT_PORT_BITMAP +#define NETC_SOC_INPUT_FRM_SWT_PORT_BITMAP (0x10) +#endif /*! @brief Defines the NETC link index. */ typedef enum _netc_soc_link @@ -42,21 +54,21 @@ typedef enum _netc_soc_link typedef enum _netc_soc_revmii_mii_speed { kNETC_SocRevMiiSpeed100M = 0U, /*!< RevMII MII mode speed 100 Mbps. */ - kNETC_SocRevMiiSpeed10M, /*!< RevMII MII mode speed 10 Mbps. */ + kNETC_SocRevMiiSpeed10M, /*!< RevMII MII mode speed 10 Mbps. */ } netc_soc_revmii_mii_speed_t; /*! @brief Defines clock source for NETC timer. */ typedef enum _netc_soc_timer_clk_sel { kNETC_SocTimerCcmClk = 0U, /*!< PTP timer clock source is from CCM tmr_1588_clk_root. */ - kNETC_SocTimerExtPinClk, /*!< PTP timer clock source is from chip pin. */ + kNETC_SocTimerExtPinClk, /*!< PTP timer clock source is from chip pin. */ } netc_soc_timer_clk_sel_t; /*! @brief Defines the timer trigger input source. */ typedef enum _netc_soc_timer_trig_input { kNETC_SocTimerTrigIomuxInput = 0U, /*!< Input from IOMUX. */ - kNETC_SocTimerTrigXbarInput, /*!< Input from XBAR. */ + kNETC_SocTimerTrigXbarInput, /*!< Input from XBAR. */ } netc_soc_timer_trig_input_t; /*! @brief Station interface index enumerator */ @@ -180,12 +192,4 @@ status_t NETC_SocSetLinkAddr(netc_soc_link_t link, uint8_t phyAddr); */ uint32_t NETC_SocGetFuncInstance(netc_hw_eth_port_idx_t port); -/*! - * @brief Preinit VSIs - * - * @param hw The enetc hw handle. - * @param si The SI object. - * @return status_t - */ -status_t NETC_SocPreInitVsi(netc_enetc_hw_t *hw, netc_hw_si_idx_t si); #endif /* FSL_NETC_SOC_H_ */