From e44b2543e1e034b70e1de6b4eb91dfc30baa2720 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Thu, 6 Jan 2022 12:09:52 +0800 Subject: [PATCH 1/4] fsl_common_arm: Fix comment sign issue on different architectures The comment sign character is '//' on ARMv8 AARCH64, however it's '@' on other ARM architectures. So the current definitions of AT_NONCACHEABLE_SECTION_ALIGN and AT_NONCACHEABLE_SECTION will result in the following error on AARCH64. /tmp/cc96AQ7j.s: Assembler messages: /tmp/cc96AQ7j.s:1020: Error: junk at end of line, first unrecognized character is `@' Signed-off-by: Hou Zhiqiang Signed-off-by: Stephane Viau Signed-off-by: Jiafei Pan --- mcux/mcux-sdk-ng/drivers/common/fsl_common_arm.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/mcux/mcux-sdk-ng/drivers/common/fsl_common_arm.h b/mcux/mcux-sdk-ng/drivers/common/fsl_common_arm.h index a2dac5b737..8c0b68d8f1 100644 --- a/mcux/mcux-sdk-ng/drivers/common/fsl_common_arm.h +++ b/mcux/mcux-sdk-ng/drivers/common/fsl_common_arm.h @@ -474,15 +474,21 @@ _Pragma("diag_suppress=Pm120") #endif #elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#if defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */ +#define MCUX_CS "//" +#else +#define MCUX_CS "@" +#endif + /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" * in your projects to make sure the non-cacheable section variables will be initialized in system startup. */ #define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var #define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits " MCUX_CS))) var #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) + __attribute__((section("NonCacheable,\"aw\",%nobits " MCUX_CS))) var __attribute__((aligned(alignbytes))) #else #error Toolchain not supported. #endif From cafbc18080dbbf44292a1393d6764482770a92be Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Thu, 29 May 2025 18:25:33 +0800 Subject: [PATCH 2/4] mcux-sdk: MIMX9596_ca55: fix A-Core header file NETC driver is not compatible with struct definition, for example will report the following build error like: modules/hal/nxp/mcux/mcux-sdk-ng/drivers/netc/fsl_netc_timer.h:369:20: error: 'ENETC_PF_TMR_Type' has no member named 'TMR_TEVENT' Signed-off-by: Jiafei Pan --- mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55.h b/mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55.h index e15e78f577..5ffa2b9269 100644 --- a/mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55.h +++ b/mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55.h @@ -88899,7 +88899,6 @@ typedef struct { /** ENETC_PF_TMR - Register Layout Typedef */ typedef struct { - struct { /* offset: 0x0, array step: 0xFC */ __I uint32_t TMR_ID; /**< Module ID, array offset: 0x0, array step: 0xFC */ uint8_t RESERVED_0[4]; __I uint32_t TMR_CAPR; /**< Timer Capability, array offset: 0x8, array step: 0xFC */ @@ -88940,7 +88939,6 @@ typedef struct { __I uint32_t TMR_CUR_TIME_L; /**< Timer Current Time Low, array offset: 0xF0, array step: 0xFC */ __I uint32_t TMR_CUR_TIME_H; /**< Timer Current Time High, array offset: 0xF4, array step: 0xFC */ __IO uint32_t TMR_PARAM; /**< Timer Parameter, array offset: 0xF8, array step: 0xFC */ - } ALL_REG_ARRAYS[1]; } ENETC_PF_TMR_Type; /* ---------------------------------------------------------------------------- From 0b84ae4b07a6da49dacb52a2d7d830afcba70cf1 Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Fri, 30 May 2025 18:09:32 +0800 Subject: [PATCH 3/4] mcux-sdk: MIMX9596_ca55: disable FSL_FEATURE_NETC_HAS_ERRATA_051711 This Errata is not available on i.MX 95. Signed-off-by: Jiafei Pan --- mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55_features.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55_features.h b/mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55_features.h index c00c0f487e..441f345ae4 100644 --- a/mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55_features.h +++ b/mcux/mcux-sdk/devices/MIMX9596/MIMX9596_ca55_features.h @@ -605,7 +605,7 @@ /* @brief After one or more late collision or excessive collision events, counters PMa_TOCTn and PMa_TFRMn will be higher than expected. */ #define FSL_FEATURE_NETC_HAS_ERRATA_051710 (1) /* @brief MAC statistic counters TEOCT and TOCT are inaccurate after Pause frames are transmitted with flexible preamble enabled and flexible preamble count set to less than 7. */ -#define FSL_FEATURE_NETC_HAS_ERRATA_051711 (1) +#define FSL_FEATURE_NETC_HAS_ERRATA_051711 (0) /* @brief Number of Switch ports. */ #define FSL_FEATURE_NETC_SWITCH_MAX_PORT_NUMBER (5) /* @brief Number of Switch Ethernet MAC ports. */ From b15c20f9a1a77c89d2d5000fd3701aa48974a7de Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Thu, 29 May 2025 18:15:34 +0800 Subject: [PATCH 4/4] drivers: netc: make the driver to be aarch64 compatible Signed-off-by: Jiafei Pan --- mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c index 9010a51149..de5b392f56 100644 --- a/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c +++ b/mcux/mcux-sdk-ng/drivers/netc/netc_hw/fsl_netc_hw.c @@ -129,7 +129,7 @@ status_t NETC_CmdBDRInit(netc_cbdr_hw_t *base, const netc_cmd_bdr_config_t *conf status_t status = kStatus_Success; uint64_t address; - if ((0U != ((uint32_t)config->bdBase % 128U)) || (0U != (config->bdLength % 8U))) + if ((0U != ((uintptr_t)config->bdBase % 128U)) || (0U != (config->bdLength % 8U))) { status = kStatus_InvalidArgument; }