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hal_nxp: Sync 25.06 wireless to hal_nxp
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
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mcux/mcux-sdk-ng/devices/Wireless/K32W/K32W1480/CMakeLists.txt

Lines changed: 1 addition & 1 deletion
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@@ -5,7 +5,7 @@
55

66
#### device spepcific drivers
77
include(${SdkRootDirPath}/devices/arm/device_header.cmake)
8-
mcux_add_cmakelists(${SdkRootDirPath}/devices/Wireless/K32W/K32W1480/drivers)
8+
mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/Wireless/K32W/K32W1480/drivers)
99

1010
#### Wireless shared drivers/components/middlewares, project segments
1111
include(${SdkRootDirPath}/devices/Wireless/shared.cmake)

mcux/mcux-sdk-ng/devices/Wireless/K32W/K32W1480/K32W1480.h

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,14 +7,14 @@
77
** MCUXpresso Compiler
88
**
99
** Reference manual: Rev. 2, Jan. 6, 2022
10-
** Version: rev. 1.0, 2021-01-18
11-
** Build: b240715
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** Version: rev. 2.0, 2024-10-29
11+
** Build: b250520
1212
**
1313
** Abstract:
1414
** CMSIS Peripheral Access Layer for K32W1480
1515
**
1616
** Copyright 1997-2016 Freescale Semiconductor, Inc.
17-
** Copyright 2016-2024 NXP
17+
** Copyright 2016-2025 NXP
1818
** SPDX-License-Identifier: BSD-3-Clause
1919
**
2020
** http: www.nxp.com
@@ -23,14 +23,17 @@
2323
** Revisions:
2424
** - rev. 1.0 (2021-01-18)
2525
** Initial version.
26+
** - rev. 2.0 (2024-10-29)
27+
** Change the device header file from single flat file to multiple files based on peripherals,
28+
** each peripheral with dedicated header file located in periphN folder.
2629
**
2730
** ###################################################################
2831
*/
2932

3033
/*!
3134
* @file K32W1480.h
32-
* @version 1.0
33-
* @date 2021-01-18
35+
* @version 2.0
36+
* @date 2024-10-29
3437
* @brief CMSIS Peripheral Access Layer for K32W1480
3538
*
3639
* CMSIS Peripheral Access Layer for K32W1480

mcux/mcux-sdk-ng/devices/Wireless/K32W/K32W1480/K32W1480_COMMON.h

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -7,14 +7,14 @@
77
** MCUXpresso Compiler
88
**
99
** Reference manual: Rev. 2, Jan. 6, 2022
10-
** Version: rev. 1.0, 2021-01-18
11-
** Build: b240715
10+
** Version: rev. 2.0, 2024-10-29
11+
** Build: b250520
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**
1313
** Abstract:
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** CMSIS Peripheral Access Layer for K32W1480
1515
**
1616
** Copyright 1997-2016 Freescale Semiconductor, Inc.
17-
** Copyright 2016-2024 NXP
17+
** Copyright 2016-2025 NXP
1818
** SPDX-License-Identifier: BSD-3-Clause
1919
**
2020
** http: www.nxp.com
@@ -23,14 +23,17 @@
2323
** Revisions:
2424
** - rev. 1.0 (2021-01-18)
2525
** Initial version.
26+
** - rev. 2.0 (2024-10-29)
27+
** Change the device header file from single flat file to multiple files based on peripherals,
28+
** each peripheral with dedicated header file located in periphN folder.
2629
**
2730
** ###################################################################
2831
*/
2932

3033
/*!
3134
* @file K32W1480_COMMON.h
32-
* @version 1.0
33-
* @date 2021-01-18
35+
* @version 2.0
36+
* @date 2024-10-29
3437
* @brief CMSIS Peripheral Access Layer for K32W1480
3538
*
3639
* CMSIS Peripheral Access Layer for K32W1480
@@ -41,7 +44,7 @@
4144

4245
/** Memory map major version (memory maps with equal major version number are
4346
* compatible) */
44-
#define MCU_MEM_MAP_VERSION 0x0100U
47+
#define MCU_MEM_MAP_VERSION 0x0200U
4548
/** Memory map minor version */
4649
#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
4750

@@ -176,15 +179,17 @@ typedef enum IRQn {
176179
#include "core_cm33.h" /* Core Peripheral Access Layer */
177180
#include "system_K32W1480.h" /* Device specific configuration file */
178181

179-
#define K32W1480_SERIES
180-
/* CPU specific feature definitions */
181-
#include "K32W1480_features.h"
182-
183182
/*!
184183
* @}
185184
*/ /* end of group Cortex_Core_Configuration */
186185

187186

187+
#ifndef K32W1480_SERIES
188+
#define K32W1480_SERIES
189+
#endif
190+
/* CPU specific feature definitions */
191+
#include "K32W1480_features.h"
192+
188193
/* ADC - Peripheral instance base addresses */
189194
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
190195
/** Peripheral ADC0 base address */

mcux/mcux-sdk-ng/devices/Wireless/K32W/K32W1480/K32W1480_features.h

Lines changed: 35 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
11
/*
22
** ###################################################################
33
** Version: rev. 1.0, 2021-01-18
4-
** Build: b240414
4+
** Build: b250512
55
**
66
** Abstract:
77
** Chip specific module features.
88
**
99
** Copyright 2016 Freescale Semiconductor, Inc.
10-
** Copyright 2016-2024 NXP
10+
** Copyright 2016-2025 NXP
1111
** SPDX-License-Identifier: BSD-3-Clause
1212
**
1313
** http: www.nxp.com
@@ -110,8 +110,6 @@
110110
#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
111111
/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
112112
#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
113-
/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
114-
#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
115113
/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
116114
#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
117115
/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
@@ -128,10 +126,6 @@
128126
#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
129127
/* @brief Has offset trim (register OFSTRIM). */
130128
#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
131-
/* @brief OFSTRIM availability on the SoC. */
132-
#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2)
133-
/* @brief Has Trigger status register. */
134-
#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
135129
/* @brief Has power select (bitfield CFG[PWRSEL]). */
136130
#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
137131
/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
@@ -144,6 +138,12 @@
144138
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
145139
/* @brief Conversion averaged bitfiled width. */
146140
#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
141+
/* @brief Enable hardware trigger command selection */
142+
#define FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL (0)
143+
/* @brief OFSTRIM availability on the SoC. */
144+
#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2)
145+
/* @brief Has Trigger status register. */
146+
#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
147147
/* @brief Has B side channels. */
148148
#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1)
149149
/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */
@@ -166,6 +166,10 @@
166166
#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1)
167167
/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */
168168
#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2)
169+
/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
170+
#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
171+
/* @brief Has High Speed Mode Trim Request (bitfield CTRL[CALHS]). */
172+
#define FSL_FEATURE_LPADC_HAS_CTRL_CALHS (0)
169173
/* @brief Has internal temperature sensor. */
170174
#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
171175
/* @brief Temperature sensor parameter A (slope). */
@@ -238,12 +242,14 @@
238242

239243
/* FLEXIO module features */
240244

245+
/* @brief Has DOZEN bit(CTRL[DOZEN]) */
246+
#define FSL_FEATURE_FLEXIO_HAS_DOZE_MODE_SUPPORT (1)
247+
/* @brief FLEXIO support reset from RSTCTL */
248+
#define FSL_FEATURE_FLEXIO_HAS_RESET (0)
241249
/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
242250
#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
243251
/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
244252
#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
245-
/* @brief Has pin input output related registers */
246-
#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1)
247253
/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
248254
#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
249255
/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
@@ -260,8 +266,12 @@
260266
#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003)
261267
/* @brief Reset value of the FLEXIO_PARAM register */
262268
#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200808)
269+
/* @brief Flexio DMA request base channel */
270+
#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0)
263271
/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */
264272
#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3)
273+
/* @brief Has pin input output related registers */
274+
#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1)
265275

266276
/* MSF1 module features */
267277

@@ -325,6 +335,8 @@
325335
#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
326336
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
327337
#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
338+
/* @brief Has dedicated interrupt for master and slave. */
339+
#define FSL_FEATURE_LPI2C_HAS_ROLE_SPLIT_IRQ (0)
328340

329341
/* LPIT module features */
330342

@@ -337,15 +349,15 @@
337349

338350
/* LPSPI module features */
339351

340-
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
352+
/* @brief Capacity (number of entries) of the transmit/receive FIFO. */
341353
#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8)
342354
/* @brief Has separate DMA RX and TX requests. */
343355
#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
344356
/* @brief Has CCR1 (related to existence of registers CCR1). */
345357
#define FSL_FEATURE_LPSPI_HAS_CCR1 (1)
346-
/* @brief Has no PCSCFG bit in CFGR1 register */
358+
/* @brief Has no PCSCFG bit in CFGR1 register. */
347359
#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0)
348-
/* @brief Has no WIDTH bits in TCR register */
360+
/* @brief Has no WIDTH bits in TCR register. */
349361
#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0)
350362

351363
/* LPTMR module features */
@@ -431,12 +443,16 @@
431443
#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
432444
/* @brief Has LPUART_PINCFG. */
433445
#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
446+
/* @brief Belong to LPFLEXCOMM */
447+
#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (0)
434448
/* @brief Has register MODEM Control. */
435449
#define FSL_FEATURE_LPUART_HAS_MCR (0)
436450
/* @brief Has register Half Duplex Control. */
437451
#define FSL_FEATURE_LPUART_HAS_HDCR (0)
438452
/* @brief Has register Timeout. */
439453
#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0)
454+
/* @brief UART support swap TX and RX (has bit CTRL[SWAP]). */
455+
#define FSL_FEATURE_LPUART_HAS_CTRL_SWAP (0)
440456

441457
/* LTC module features */
442458

@@ -621,10 +637,10 @@
621637
(((x) == TPM2) ? (0) : (-1))))
622638
/* @brief Has global time base enable. */
623639
#define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_EN (1)
624-
/* @brief Has counter pause on trigger. */
625-
#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
626640
/* @brief Has global time base sync. */
627641
#define FSL_FEATURE_TPM_HAS_GLOBAL_TIME_BASE_SYNC (1)
642+
/* @brief Has counter pause on trigger. */
643+
#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
628644
/* @brief Has external trigger selection. */
629645
#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
630646
/* @brief Has TPM_COMBINE register. */
@@ -635,9 +651,9 @@
635651
#define FSL_FEATURE_TPM_HAS_POL (1)
636652
/* @brief Whether POL register has effect. */
637653
#define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) \
638-
(((x) == TPM2) ? (0) : \
639654
(((x) == TPM0) ? (1) : \
640-
(((x) == TPM1) ? (1) : (-1))))
655+
(((x) == TPM1) ? (1) : \
656+
(((x) == TPM2) ? (0) : (-1))))
641657
/* @brief Has TPM_FILTER register. */
642658
#define FSL_FEATURE_TPM_HAS_FILTER (1)
643659
/* @brief Whether FILTER register has effect. */
@@ -646,9 +662,9 @@
646662
#define FSL_FEATURE_TPM_HAS_QDCTRL (1)
647663
/* @brief Whether QDCTRL register has effect. */
648664
#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \
649-
(((x) == TPM2) ? (0) : \
650665
(((x) == TPM0) ? (1) : \
651-
(((x) == TPM1) ? (1) : (-1))))
666+
(((x) == TPM1) ? (1) : \
667+
(((x) == TPM2) ? (0) : (-1))))
652668
/* @brief Has pause level select. */
653669
#define FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT (1)
654670
/* @brief Whether 32 bits counter has effect. */

mcux/mcux-sdk-ng/devices/Wireless/K32W/K32W1480/drivers/CMakeLists.txt

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
1-
# Copyright 2024 NXP
1+
# Copyright 2024-2025 NXP
22
#
33
#
44
# SPDX-License-Identifier: BSD-3-Clause
55

66
if (CONFIG_MCUX_COMPONENT_driver.clock)
7-
mcux_component_version(2.2.1)
7+
mcux_component_version(2.2.2)
88

99
mcux_add_source( SOURCES fsl_clock.c fsl_clock.h )
1010
mcux_add_include( INCLUDES . )

mcux/mcux-sdk-ng/devices/Wireless/K32W/K32W1480/drivers/fsl_clock.h

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2021-2022 NXP
2+
* Copyright 2021-2022,2025 NXP
33
*
44
*
55
* SPDX-License-Identifier: BSD-3-Clause
@@ -39,8 +39,8 @@
3939

4040
/*! @name Driver version */
4141
/*@{*/
42-
/*! @brief CLOCK driver version 1.0.0. */
43-
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
42+
/*! @brief CLOCK driver version 2.2.2. */
43+
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
4444
/*@}*/
4545

4646
/* Definition for delay API in clock driver, users can redefine it to the real application. */
@@ -1129,6 +1129,20 @@ static inline void CLOCK_UnlockFircControlStatusReg(void)
11291129
CLOCK_REG(&SCG0->FIRCCSR) &= ~(SCG_FIRCCSR_LK_MASK);
11301130
}
11311131

1132+
/*!
1133+
* @brief Check whether FIRC auto trim locked to target frequency range.
1134+
*
1135+
* When FIRCTREN and FIRCTRUP are enabled, TRIM_LOCK will indicate when auto
1136+
* trimming is complete and output FIRC frequency has locked to target FIRC range.
1137+
* TRIM_LOCK will automatically get cleared if FIRCTREN and FIRCTRUP are not set.
1138+
*
1139+
* @return True if FIRC trim locked to target frequency range, false if not.
1140+
*/
1141+
static inline bool CLOCK_IsFIRCAutoTrimLocked(void)
1142+
{
1143+
return ((bool)(CLOCK_REG(&SCG0->FIRCCSR) & SCG_FIRCCSR_TRIM_LOCK_MASK));
1144+
}
1145+
11321146
/*!
11331147
* @brief Lock the FIRCCSR control status register.
11341148
*/

mcux/mcux-sdk-ng/devices/Wireless/K32W/K32W1480/fsl_device_registers.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright 2014-2016 Freescale Semiconductor, Inc.
3-
* Copyright 2016-2024 NXP
3+
* Copyright 2016-2025 NXP
44
* SPDX-License-Identifier: BSD-3-Clause
55
*
66
*/

mcux/mcux-sdk-ng/devices/Wireless/K32W/K32W1480/internal/fsl_device_registers.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,9 @@
1717
*/
1818
#if (defined(CPU_K32W1480VFTA))
1919

20+
#ifndef K32W1480_SERIES
2021
#define K32W1480_SERIES
22+
#endif
2123

2224
/* CMSIS-style register definitions */
2325
#include "K32W1480.h"

mcux/mcux-sdk-ng/devices/Wireless/K32W/K32W1480/system_K32W1480.c

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,16 +7,16 @@
77
** MCUXpresso Compiler
88
**
99
** Reference manual: Rev. 2, Jan. 6, 2022
10-
** Version: rev. 1.0, 2021-01-18
11-
** Build: b240227
10+
** Version: rev. 2.0, 2024-10-29
11+
** Build: b250520
1212
**
1313
** Abstract:
1414
** Provides a system configuration function and a global variable that
1515
** contains the system frequency. It configures the device and initializes
1616
** the oscillator (PLL) that is part of the microcontroller device.
1717
**
1818
** Copyright 2016 Freescale Semiconductor, Inc.
19-
** Copyright 2016-2024 NXP
19+
** Copyright 2016-2025 NXP
2020
** SPDX-License-Identifier: BSD-3-Clause
2121
**
2222
** http: www.nxp.com
@@ -25,14 +25,17 @@
2525
** Revisions:
2626
** - rev. 1.0 (2021-01-18)
2727
** Initial version.
28+
** - rev. 2.0 (2024-10-29)
29+
** Change the device header file from single flat file to multiple files based on peripherals,
30+
** each peripheral with dedicated header file located in periphN folder.
2831
**
2932
** ###################################################################
3033
*/
3134

3235
/*!
3336
* @file K32W1480
34-
* @version 1.0
35-
* @date 2021-01-18
37+
* @version 2.0
38+
* @date 2024-10-29
3639
* @brief Device specific configuration file for K32W1480 (implementation file)
3740
*
3841
* Provides a system configuration function and a global variable that contains

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