s32: mcux: S32Z270: add missing flexcan features on s32z27x devices

add memory error control features and remove some bits is unsupported
on s32z27x devices

Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>

Author: tunguyen4585

s32/mcux/devices/S32Z270/S32Z270_device.h

@@ -130,11 +130,6 @@ typedef struct {
 
 #define CAN_MCR_SRXDIS(x) FLEXCAN_MCR_SRXDIS(x)
 
-#define CAN_MCR_WAKSRC_MASK  (0x80000U)
-#define CAN_MCR_WAKSRC_SHIFT (19U)
-
-#define CAN_MCR_WAKSRC(x) FLEXCAN_MCR_WAKSRC(x)
-
 #define CAN_MCR_LPMACK_MASK  FLEXCAN_MCR_LPMACK_MASK
 #define CAN_MCR_LPMACK_SHIFT FLEXCAN_MCR_LPMACK_SHIFT
 
@@ -145,11 +140,6 @@ typedef struct {
 
 #define CAN_MCR_WRNEN(x) FLEXCAN_MCR_WRNEN(x)
 
-#define CAN_MCR_SLFWAK_MASK  (0x400000U)
-#define CAN_MCR_SLFWAK_SHIFT (22U)
-
-#define CAN_MCR_SLFWAK(x) FLEXCAN_MCR_SLFWAK(x)
-
 #define CAN_MCR_FRZACK_MASK  FLEXCAN_MCR_FRZACK_MASK
 #define CAN_MCR_FRZACK_SHIFT FLEXCAN_MCR_FRZACK_SHIFT
 
@@ -160,11 +150,6 @@ typedef struct {
 
 #define CAN_MCR_SOFTRST(x) FLEXCAN_MCR_SOFTRST(x)
 
-#define CAN_MCR_WAKMSK_MASK  (0x4000000U)
-#define CAN_MCR_WAKMSK_SHIFT (26U)
-
-#define CAN_MCR_WAKMSK(x) FLEXCAN_MCR_WAKMSK(x)
-
 #define CAN_MCR_NOTRDY_MASK  FLEXCAN_MCR_NOTRDY_MASK
 #define CAN_MCR_NOTRDY_SHIFT FLEXCAN_MCR_NOTRDY_SHIFT
 
@@ -333,11 +318,6 @@ typedef struct {
 /*! @name ESR1 - Error and Status 1 Register */
 /*! @{ */
 
-#define CAN_ESR1_WAKINT_MASK  (0x1U)
-#define CAN_ESR1_WAKINT_SHIFT (0U)
-
-#define CAN_ESR1_WAKINT(x) FLEXCAN_ESR1_WAKINT(x)
-
 #define CAN_ESR1_ERRINT_MASK  FLEXCAN_ESR1_ERRINT_MASK
 #define CAN_ESR1_ERRINT_SHIFT FLEXCAN_ESR1_ERRINT_SHIFT
 

s32/mcux/devices/S32Z270/S32Z270_features.h

@@ -81,7 +81,15 @@
 /* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */
 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1)
 /* @brief Has memory error control (register MECR). */
-#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0)
+#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (1)
+/* @brief Init memory base 1 */
+#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1 (0x80)
+/* @brief Init memory size 1 */
+#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 (0xA60)
+/* @brief Init memory base 2 */
+#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2 (0xC20)
+/* @brief Init memory size 2 */
+#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 (0x25E0)
 /* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */
 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (0)
 /* @brief Has Pretended Networking mode support. */
@@ -90,6 +98,18 @@
 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (0)
 /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */
 #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1)
+/* @brief Does not support Memory Error Control (bitfield MECR[HANCEI]. */
+#define FSL_FEATURE_FLEXCAN_HAS_NO_HANCEI_SUPPORT (1)
+/* @brief Does not support Memory Error Control (bitfield MECR[FANCEI]. */
+#define FSL_FEATURE_FLEXCAN_HAS_NO_FANCEI_SUPPORT (1)
+/* @brief Does not support Memory Error Control (bitfield MECR[CEI]. */
+#define FSL_FEATURE_FLEXCAN_HAS_NO_CEI_SUPPORT (1)
+/* @brief Does not support Wake Up interrupt (bitfield MCR[WAKMSK]. */
+#define FSL_FEATURE_FLEXCAN_HAS_NO_WAKMSK_SUPPORT (1)
+/* @brief Does not support Self Wake Up (bitfield MCR[SLFWAK]. */
+#define FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT (1)
+/* @brief Does not support Wake Up Source (bitfield MCR[WAKSRC]. */
+#define FSL_FEATURE_FLEXCAN_HAS_NO_WAKSRC_SUPPORT (1)
 
 /* I2C module features */