hal_nxp: Sync 25.06 Kinetis to hal_nxp

Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>

Author: ZhaoxiangJin

mcux/mcux-sdk-ng/devices/Kinetis/K/MK02F12810/CMakeLists.txt

@@ -5,7 +5,7 @@
 
 #### device spepcific drivers
 include(${SdkRootDirPath}/devices/arm/device_header.cmake)
-mcux_add_cmakelists(${SdkRootDirPath}/devices/Kinetis/K/MK02F12810/drivers)
+mcux_add_cmakelists(${SdkRootDirPath}/${device_root}/Kinetis/K/MK02F12810/drivers)
 
 #### Kinetis shared drivers/components/middlewares, project segments
 include(${SdkRootDirPath}/devices/Kinetis/shared.cmake)

mcux/mcux-sdk-ng/devices/Kinetis/K/MK02F12810/MK02F12810.h

@@ -14,14 +14,14 @@
 **                          MCUXpresso Compiler
 **
 **     Reference manual:    K02P64M100SFARM, Rev. 0, February 14, 2014
-**     Version:             rev. 0.5, 2015-02-19
-**     Build:               b240710
+**     Version:             rev. 1.0, 2024-10-29
+**     Build:               b250520
 **
 **     Abstract:
 **         CMSIS Peripheral Access Layer for MK02F12810
 **
 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2024 NXP
+**     Copyright 2016-2025 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -40,14 +40,17 @@
 **         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
 **     - rev. 0.5 (2015-02-19)
 **         Renamed interrupt vector LLW to LLWU.
+**     - rev. 1.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
 **
 ** ###################################################################
 */
 
 /*!
  * @file MK02F12810.h
- * @version 0.5
- * @date 2015-02-19
+ * @version 1.0
+ * @date 2024-10-29
  * @brief CMSIS Peripheral Access Layer for MK02F12810
  *
  * CMSIS Peripheral Access Layer for MK02F12810

mcux/mcux-sdk-ng/devices/Kinetis/K/MK02F12810/MK02F12810_COMMON.h

@@ -14,14 +14,14 @@
 **                          MCUXpresso Compiler
 **
 **     Reference manual:    K02P64M100SFARM, Rev. 0, February 14, 2014
-**     Version:             rev. 0.5, 2015-02-19
-**     Build:               b240710
+**     Version:             rev. 1.0, 2024-10-29
+**     Build:               b250520
 **
 **     Abstract:
 **         CMSIS Peripheral Access Layer for MK02F12810
 **
 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2024 NXP
+**     Copyright 2016-2025 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -40,14 +40,17 @@
 **         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
 **     - rev. 0.5 (2015-02-19)
 **         Renamed interrupt vector LLW to LLWU.
+**     - rev. 1.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
 **
 ** ###################################################################
 */
 
 /*!
  * @file MK02F12810_COMMON.h
- * @version 0.5
- * @date 2015-02-19
+ * @version 1.0
+ * @date 2024-10-29
  * @brief CMSIS Peripheral Access Layer for MK02F12810
  *
  * CMSIS Peripheral Access Layer for MK02F12810
@@ -58,9 +61,9 @@
 
 /** Memory map major version (memory maps with equal major version number are
  * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0000U
+#define MCU_MEM_MAP_VERSION 0x0100U
 /** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0005U
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
 
 /**
  * @brief Macro to calculate address of an aliased word in the peripheral
@@ -226,15 +229,17 @@ typedef enum IRQn {
 #include "core_cm4.h"                  /* Core Peripheral Access Layer */
 #include "system_MK02F12810.h"         /* Device specific configuration file */
 
-#define MK02F12810_SERIES
-/* CPU specific feature definitions */
-#include "MK02F12810_features.h"
-
 /*!
  * @}
  */ /* end of group Cortex_Core_Configuration */
 
 
+#ifndef MK02F12810_SERIES
+#define MK02F12810_SERIES
+#endif
+/* CPU specific feature definitions */
+#include "MK02F12810_features.h"
+
 /* ADC - Peripheral instance base addresses */
 /** Peripheral ADC0 base address */
 #define ADC0_BASE                                (0x4003B000u)

mcux/mcux-sdk-ng/devices/Kinetis/K/MK02F12810/MK02F12810_features.h

@@ -1,13 +1,13 @@
 /*
 ** ###################################################################
 **     Version:             rev. 0.9, 2015-06-08
-**     Build:               b240417
+**     Build:               b250324
 **
 **     Abstract:
 **         Chip specific module features.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2024 NXP
+**     Copyright 2016-2025 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -632,6 +632,28 @@
 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0)
 /* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */
 #define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (0)
+/* @brief Has filter prescaler. */
+#define FSL_FEATURE_FTM_HAS_FILTER_PRESCALER (0)
+/* @brief Has fault output state configurable. */
+#define FSL_FEATURE_FTM_HAS_FAULT_OUTPUT_STATE (0)
+/* @brief Has paired deadtime. */
+#define FSL_FEATURE_FTM_HAS_PAIRED_DEADTIME (0)
+/* @brief Has PWM dithering. */
+#define FSL_FEATURE_FTM_HAS_DITHERING (0)
+/* @brief FTM instance has PWM dithering. */
+#define FSL_FEATURE_FTM_INSTANCE_HAS_DITHERINGn(x) (0)
+/* @brief Has trigger mode control. */
+#define FSL_FEATURE_FTM_HAS_TRIGGER_MODE (0)
+/* @brief Has modified combine mode. */
+#define FSL_FEATURE_FTM_HAS_MODIFIED_COMBINE_PWM (0)
+/* @brief Has configurable channel input state. */
+#define FSL_FEATURE_FTM_HAS_CONF_CHIS_BIT (0)
+/* @brief Has configurable channel output value. */
+#define FSL_FEATURE_FTM_HAS_CONF_CHOV_BIT (0)
+/* @brief FTM instance has Quadrature Decoder with input filter. */
+#define FSL_FEATURE_FTM_INSTANCE_HAS_QUAD_DECODEn(x) (1)
+/* @brief FTM instance fault input number. */
+#define FSL_FEATURE_FTM_INSTANCE_FAULT_INPUT_NUMBERn(x) (4)
 
 /* GPIO module features */
 
@@ -1493,6 +1515,8 @@
 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
 /* @brief Has timer enable control. */
 #define FSL_FEATURE_PIT_HAS_MDIS (1)
+/* @brief Has ERRATA 7914. */
+#define FSL_FEATURE_PIT_HAS_ERRATA_7914 (0)
 
 /* PMC module features */
 

mcux/mcux-sdk-ng/devices/Kinetis/K/MK02F12810/fsl_device_registers.h

@@ -1,6 +1,6 @@
 /*
  * Copyright 2014-2016 Freescale Semiconductor, Inc.
- * Copyright 2016-2024 NXP
+ * Copyright 2016-2025 NXP
  * SPDX-License-Identifier: BSD-3-Clause
  *
  */

mcux/mcux-sdk-ng/devices/Kinetis/K/MK02F12810/system_MK02F12810.c

@@ -14,16 +14,16 @@
 **                          MCUXpresso Compiler
 **
 **     Reference manual:    K02P64M100SFARM, Rev. 0, February 14, 2014
-**     Version:             rev. 0.5, 2015-02-19
-**     Build:               b240710
+**     Version:             rev. 1.0, 2024-10-29
+**     Build:               b250520
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2024 NXP
+**     Copyright 2016-2025 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -42,14 +42,17 @@
 **         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
 **     - rev. 0.5 (2015-02-19)
 **         Renamed interrupt vector LLW to LLWU.
+**     - rev. 1.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
 **
 ** ###################################################################
 */
 
 /*!
  * @file MK02F12810
- * @version 0.5
- * @date 2015-02-19
+ * @version 1.0
+ * @date 2024-10-29
  * @brief Device specific configuration file for MK02F12810 (implementation file)
  *
  * Provides a system configuration function and a global variable that contains
@@ -100,7 +103,7 @@ void SystemInit (void) {
 
 void SystemCoreClockUpdate (void) {
 
-  uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
+  uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
   uint16_t Divider;
   uint8_t tmpC7 = 0;
 
@@ -110,11 +113,11 @@ void SystemCoreClockUpdate (void) {
       /* External reference clock is selected */
       switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
       case 0x00U:
-        MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
+        MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
         break;
       case 0x02U:
       default:
-        MCGOUTClock = CPU_INT_IRC_CLK_HZ;                                              /* IRC 48MHz oscillator drives MCG clock */
+        MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
         break;
       }
       tmpC7 = MCG->C7;
@@ -130,14 +133,14 @@ void SystemCoreClockUpdate (void) {
           Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
           break;
         }
-      } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+      } else {
         Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
       }
-      MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
-    } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
-      MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
-    } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
-    /* Select correct multiplier to calculate the MCG output clock  */
+      MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+    } else {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+    }
+    /* Select correct multiplier to calculate the MCG output clock */
     switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
       case 0x00U:
         MCGOUTClock *= 640U;
@@ -170,26 +173,26 @@ void SystemCoreClockUpdate (void) {
   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
     /* Internal reference clock is selected */
     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
-      MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
-    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+    } else { /* Fast internal reference clock selected */
       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
-      MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider);  /* Fast internal reference clock selected */
-    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+      MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider);
+    }
   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
     /* External reference clock is selected */
     switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
     case 0x00U:
-      MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
+      MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
       break;
     case 0x02U:
     default:
-      MCGOUTClock = CPU_INT_IRC_CLK_HZ;                                              /* IRC 48MHz oscillator drives MCG clock */
+      MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
       break;
     }
-  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+  } else {
     /* Reserved value */
     return;
-  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+  }
   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
 }
 

mcux/mcux-sdk-ng/devices/Kinetis/K/MK02F12810/system_MK02F12810.h

@@ -14,16 +14,16 @@
 **                          MCUXpresso Compiler
 **
 **     Reference manual:    K02P64M100SFARM, Rev. 0, February 14, 2014
-**     Version:             rev. 0.5, 2015-02-19
-**     Build:               b240710
+**     Version:             rev. 1.0, 2024-10-29
+**     Build:               b250520
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2024 NXP
+**     Copyright 2016-2025 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -42,14 +42,17 @@
 **         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
 **     - rev. 0.5 (2015-02-19)
 **         Renamed interrupt vector LLW to LLWU.
+**     - rev. 1.0 (2024-10-29)
+**         Change the device header file from single flat file to multiple files based on peripherals,
+**         each peripheral with dedicated header file located in periphN folder.
 **
 ** ###################################################################
 */
 
 /*!
  * @file MK02F12810
- * @version 0.5
- * @date 2015-02-19
+ * @version 1.0
+ * @date 2024-10-29
  * @brief Device specific configuration file for MK02F12810 (header file)
  *
  * Provides a system configuration function and a global variable that contains
@@ -68,24 +71,24 @@ extern "C" {
 
 
 #ifndef DISABLE_WDOG
-  #define DISABLE_WDOG                 1
+  #define DISABLE_WDOG  1
 #endif
 
 /* Define clock source values */
-
-#define CPU_XTAL_CLK_HZ                8000000u            /* Value of the external crystal or oscillator clock frequency in Hz */
-#define CPU_XTAL32k_CLK_HZ             0u                  /* No RTC clock available */
-#define CPU_INT_SLOW_CLK_HZ            32768u              /* Value of the slow internal oscillator clock frequency in Hz  */
-#define CPU_INT_FAST_CLK_HZ            4000000u            /* Value of the fast internal oscillator clock frequency in Hz  */
-#define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
+#define CPU_XTAL_CLK_HZ                8000000U            /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_XTAL32k_CLK_HZ             0U                  /* No RTC clock available */
+#define CPU_INT_SLOW_CLK_HZ            32768U              /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ            4000000U            /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ             48000000U           /* Value of the 48M internal oscillator clock frequency in Hz */
 
 /* RTC oscillator setting */
 
 /* Low power mode enable */
 /* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
 #define SYSTEM_SMC_PMPROT_VALUE        0xAAU               /* SMC_PMPROT */
 
-#define DEFAULT_SYSTEM_CLOCK           20971520u           /* Default System clock value */
+#define DEFAULT_SYSTEM_CLOCK           20971520U           /* Default System clock value */
+
 
 
 /**