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mmahadevan108
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dleach02
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mcux-sdk: devices: Update CACHE64 macros for the updated driver
Update CACHE64 macros for the updated SDK driver Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
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8 files changed

+58
-42
lines changed

8 files changed

+58
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lines changed

‎mcux/mcux-sdk/devices/MCXN546/MCXN546_cm33_core0.h

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8207,20 +8207,22 @@ typedef struct {
82078207
/** Array initializer of CACHE64_CTRL peripheral base pointers */
82088208
#define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 }
82098209
#endif
8210+
/** CACHE64_CTRL physical memory base alias count */
8211+
#define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3)
82108212
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82118213
/** CACHE64_CTRL physical memory base address */
8212-
#define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x90000000u, 0xB0000000u}
8214+
#define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} }
82138215
/** CACHE64_CTRL physical memory size */
8214-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8216+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82158217
/** CACHE64_CTRL physical memory base address */
8216-
#define CACHE64_CTRL_PHYMEM_BASES_NS { 0x08000000u, 0x80000000u, 0xA0000000u}
8218+
#define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} }
82178219
/** CACHE64_CTRL physical memory size */
8218-
#define CACHE64_CTRL_PHYMEM_SIZES_NS { 0x08000000u, 0x10000000u, 0x10000000u}
8220+
#define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} }
82198221
#else
82208222
/** CACHE64_CTRL physical memory base address */
8221-
#define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x80000000u, 0xA0000000u}
8223+
#define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} }
82228224
/** CACHE64_CTRL physical memory size */
8223-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8225+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82248226
#endif
82258227
/* Backward compatibility */
82268228

‎mcux/mcux-sdk/devices/MCXN546/MCXN546_cm33_core1.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8207,6 +8207,8 @@ typedef struct {
82078207
/** Array initializer of CACHE64_CTRL peripheral base pointers */
82088208
#define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 }
82098209
#endif
8210+
/** CACHE64_CTRL physical memory base alias count */
8211+
#define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3)
82108212
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82118213
/** CACHE64_CTRL physical memory base address */
82128214
#define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x90000000u, 0xB0000000u}

‎mcux/mcux-sdk/devices/MCXN547/MCXN547_cm33_core0.h

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8207,20 +8207,22 @@ typedef struct {
82078207
/** Array initializer of CACHE64_CTRL peripheral base pointers */
82088208
#define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 }
82098209
#endif
8210+
/** CACHE64_CTRL physical memory base alias count */
8211+
#define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3)
82108212
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82118213
/** CACHE64_CTRL physical memory base address */
8212-
#define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x90000000u, 0xB0000000u}
8214+
#define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} }
82138215
/** CACHE64_CTRL physical memory size */
8214-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8216+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82158217
/** CACHE64_CTRL physical memory base address */
8216-
#define CACHE64_CTRL_PHYMEM_BASES_NS { 0x08000000u, 0x80000000u, 0xA0000000u}
8218+
#define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} }
82178219
/** CACHE64_CTRL physical memory size */
8218-
#define CACHE64_CTRL_PHYMEM_SIZES_NS { 0x08000000u, 0x10000000u, 0x10000000u}
8220+
#define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} }
82198221
#else
82208222
/** CACHE64_CTRL physical memory base address */
8221-
#define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x80000000u, 0xA0000000u}
8223+
#define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} }
82228224
/** CACHE64_CTRL physical memory size */
8223-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8225+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82248226
#endif
82258227
/* Backward compatibility */
82268228

‎mcux/mcux-sdk/devices/MCXN547/MCXN547_cm33_core1.h

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8207,20 +8207,22 @@ typedef struct {
82078207
/** Array initializer of CACHE64_CTRL peripheral base pointers */
82088208
#define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 }
82098209
#endif
8210+
/** CACHE64_CTRL physical memory base alias count */
8211+
#define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3)
82108212
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82118213
/** CACHE64_CTRL physical memory base address */
8212-
#define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x90000000u, 0xB0000000u}
8214+
#define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} }
82138215
/** CACHE64_CTRL physical memory size */
8214-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8216+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82158217
/** CACHE64_CTRL physical memory base address */
8216-
#define CACHE64_CTRL_PHYMEM_BASES_NS { 0x08000000u, 0x80000000u, 0xA0000000u}
8218+
#define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} }
82178219
/** CACHE64_CTRL physical memory size */
8218-
#define CACHE64_CTRL_PHYMEM_SIZES_NS { 0x08000000u, 0x10000000u, 0x10000000u}
8220+
#define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} }
82198221
#else
82208222
/** CACHE64_CTRL physical memory base address */
8221-
#define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x80000000u, 0xA0000000u}
8223+
#define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} }
82228224
/** CACHE64_CTRL physical memory size */
8223-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8225+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82248226
#endif
82258227
/* Backward compatibility */
82268228

‎mcux/mcux-sdk/devices/MCXN946/MCXN946_cm33_core0.h

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8241,20 +8241,22 @@ typedef struct {
82418241
/** Array initializer of CACHE64_CTRL peripheral base pointers */
82428242
#define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 }
82438243
#endif
8244+
/** CACHE64_CTRL physical memory base alias count */
8245+
#define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3)
82448246
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82458247
/** CACHE64_CTRL physical memory base address */
8246-
#define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x90000000u, 0xB0000000u}
8248+
#define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} }
82478249
/** CACHE64_CTRL physical memory size */
8248-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8250+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82498251
/** CACHE64_CTRL physical memory base address */
8250-
#define CACHE64_CTRL_PHYMEM_BASES_NS { 0x08000000u, 0x80000000u, 0xA0000000u}
8252+
#define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} }
82518253
/** CACHE64_CTRL physical memory size */
8252-
#define CACHE64_CTRL_PHYMEM_SIZES_NS { 0x08000000u, 0x10000000u, 0x10000000u}
8254+
#define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} }
82538255
#else
82548256
/** CACHE64_CTRL physical memory base address */
8255-
#define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x80000000u, 0xA0000000u}
8257+
#define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} }
82568258
/** CACHE64_CTRL physical memory size */
8257-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8259+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82588260
#endif
82598261
/* Backward compatibility */
82608262

‎mcux/mcux-sdk/devices/MCXN946/MCXN946_cm33_core1.h

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8241,20 +8241,22 @@ typedef struct {
82418241
/** Array initializer of CACHE64_CTRL peripheral base pointers */
82428242
#define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 }
82438243
#endif
8244+
/** CACHE64_CTRL physical memory base alias count */
8245+
#define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3)
82448246
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82458247
/** CACHE64_CTRL physical memory base address */
8246-
#define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x90000000u, 0xB0000000u}
8248+
#define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} }
82478249
/** CACHE64_CTRL physical memory size */
8248-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8250+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82498251
/** CACHE64_CTRL physical memory base address */
8250-
#define CACHE64_CTRL_PHYMEM_BASES_NS { 0x08000000u, 0x80000000u, 0xA0000000u}
8252+
#define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} }
82518253
/** CACHE64_CTRL physical memory size */
8252-
#define CACHE64_CTRL_PHYMEM_SIZES_NS { 0x08000000u, 0x10000000u, 0x10000000u}
8254+
#define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} }
82538255
#else
82548256
/** CACHE64_CTRL physical memory base address */
8255-
#define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x80000000u, 0xA0000000u}
8257+
#define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} }
82568258
/** CACHE64_CTRL physical memory size */
8257-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8259+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82588260
#endif
82598261
/* Backward compatibility */
82608262

‎mcux/mcux-sdk/devices/MCXN947/MCXN947_cm33_core0.h

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8241,20 +8241,22 @@ typedef struct {
82418241
/** Array initializer of CACHE64_CTRL peripheral base pointers */
82428242
#define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 }
82438243
#endif
8244+
/** CACHE64_CTRL physical memory base alias count */
8245+
#define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3)
82448246
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82458247
/** CACHE64_CTRL physical memory base address */
8246-
#define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x90000000u, 0xB0000000u}
8248+
#define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} }
82478249
/** CACHE64_CTRL physical memory size */
8248-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8250+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82498251
/** CACHE64_CTRL physical memory base address */
8250-
#define CACHE64_CTRL_PHYMEM_BASES_NS { 0x08000000u, 0x80000000u, 0xA0000000u}
8252+
#define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} }
82518253
/** CACHE64_CTRL physical memory size */
8252-
#define CACHE64_CTRL_PHYMEM_SIZES_NS { 0x08000000u, 0x10000000u, 0x10000000u}
8254+
#define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} }
82538255
#else
82548256
/** CACHE64_CTRL physical memory base address */
8255-
#define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x80000000u, 0xA0000000u}
8257+
#define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} }
82568258
/** CACHE64_CTRL physical memory size */
8257-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8259+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82588260
#endif
82598261
/* Backward compatibility */
82608262

‎mcux/mcux-sdk/devices/MCXN947/MCXN947_cm33_core1.h

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8241,20 +8241,22 @@ typedef struct {
82418241
/** Array initializer of CACHE64_CTRL peripheral base pointers */
82428242
#define CACHE64_CTRL_BASE_PTRS { CACHE64_CTRL0 }
82438243
#endif
8244+
/** CACHE64_CTRL physical memory base alias count */
8245+
#define CACHE64_CTRL_PHYMEM_BASE_ALIAS_COUNT (3)
82448246
#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2))
82458247
/** CACHE64_CTRL physical memory base address */
8246-
#define CACHE64_CTRL_PHYMEM_BASES { 0x18000000u, 0x90000000u, 0xB0000000u}
8248+
#define CACHE64_CTRL_PHYMEM_BASES { {0x18000000u, 0x90000000u, 0xB0000000u} }
82478249
/** CACHE64_CTRL physical memory size */
8248-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8250+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82498251
/** CACHE64_CTRL physical memory base address */
8250-
#define CACHE64_CTRL_PHYMEM_BASES_NS { 0x08000000u, 0x80000000u, 0xA0000000u}
8252+
#define CACHE64_CTRL_PHYMEM_BASES_NS { {0x08000000u, 0x80000000u, 0xA0000000u} }
82518253
/** CACHE64_CTRL physical memory size */
8252-
#define CACHE64_CTRL_PHYMEM_SIZES_NS { 0x08000000u, 0x10000000u, 0x10000000u}
8254+
#define CACHE64_CTRL_PHYMEM_SIZES_NS { {0x08000000u, 0x10000000u, 0x10000000u} }
82538255
#else
82548256
/** CACHE64_CTRL physical memory base address */
8255-
#define CACHE64_CTRL_PHYMEM_BASES { 0x08000000u, 0x80000000u, 0xA0000000u}
8257+
#define CACHE64_CTRL_PHYMEM_BASES { {0x08000000u, 0x80000000u, 0xA0000000u} }
82568258
/** CACHE64_CTRL physical memory size */
8257-
#define CACHE64_CTRL_PHYMEM_SIZES { 0x08000000u, 0x10000000u, 0x10000000u}
8259+
#define CACHE64_CTRL_PHYMEM_SIZES { {0x08000000u, 0x10000000u, 0x10000000u} }
82588260
#endif
82598261
/* Backward compatibility */
82608262

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