File tree Expand file tree Collapse file tree 2 files changed +30
-0
lines changed Expand file tree Collapse file tree 2 files changed +30
-0
lines changed Original file line number Diff line number Diff line change 91
91
/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */
92
92
#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1)
93
93
94
+ /* I2C module features */
95
+
96
+ /* @brief LPI2C availability on the SoC. */
97
+ #define FSL_FEATURE_SOC_LPI2C_COUNT (2)
98
+ /* @brief Has separate DMA RX and TX requests. */
99
+ #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn (x ) (1)
100
+ /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
101
+ #define FSL_FEATURE_LPI2C_FIFO_SIZEn (x ) (8)
102
+
94
103
#endif /* _S32Z270_FEATURES_H_ */
Original file line number Diff line number Diff line change 226
226
227
227
#define CAN_ORed_Message_buffer_IRQS CAN_ORed_Message_buffer_0_31_IRQS
228
228
229
+ /*!
230
+ * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
231
+ * @{
232
+ */
233
+
234
+ /* LPI2C - Peripheral instance base addresses */
235
+ /** Peripheral LPI2C1 base address */
236
+ #define LPI2C1_BASE IP_LPI2C_1_BASE
237
+ /** Peripheral LPI2C1 base pointer */
238
+ #define LPI2C1 IP_LPI2C_1
239
+ /** Peripheral LPI2C2 base address */
240
+ #define LPI2C2_BASE IP_LPI2C_2_BASE
241
+ /** Peripheral LPI2C2 base pointer */
242
+ #define LPI2C2 IP_LPI2C_2
243
+ /** Array initializer of LPI2C peripheral base addresses */
244
+ #define LPI2C_BASE_ADDRS IP_LPI2C_BASE_ADDRS
245
+ /** Array initializer of LPI2C peripheral base pointers */
246
+ #define LPI2C_BASE_PTRS IP_LPI2C_BASE_PTRS
247
+ /** Interrupt vectors for the LPI2C peripheral type */
248
+ #define LPI2C_IRQS { RTU_LPI2C1_IRQn, RTU_LPI2C2_IRQn }
249
+
229
250
#endif /* _S32Z270_GLUE_MCUX_H_ */
You can’t perform that action at this time.
0 commit comments