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s32: support LPI2C for s32z27x build with MCUX driver
Add LPI2C instance base addresses and module features to support using LPI2C MCUX driver. Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
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s32/mcux/devices/S32Z270/S32Z270_features.h

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/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */
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#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1)
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/* I2C module features */
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/* @brief LPI2C availability on the SoC. */
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#define FSL_FEATURE_SOC_LPI2C_COUNT (2)
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/* @brief Has separate DMA RX and TX requests. */
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#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
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/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
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#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8)
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#endif /* _S32Z270_FEATURES_H_ */

s32/mcux/devices/S32Z270/S32Z270_glue_mcux.h

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#define CAN_ORed_Message_buffer_IRQS CAN_ORed_Message_buffer_0_31_IRQS
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/*!
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* @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
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* @{
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*/
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/* LPI2C - Peripheral instance base addresses */
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/** Peripheral LPI2C1 base address */
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#define LPI2C1_BASE IP_LPI2C_1_BASE
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/** Peripheral LPI2C1 base pointer */
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#define LPI2C1 IP_LPI2C_1
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/** Peripheral LPI2C2 base address */
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#define LPI2C2_BASE IP_LPI2C_2_BASE
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/** Peripheral LPI2C2 base pointer */
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#define LPI2C2 IP_LPI2C_2
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/** Array initializer of LPI2C peripheral base addresses */
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#define LPI2C_BASE_ADDRS IP_LPI2C_BASE_ADDRS
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/** Array initializer of LPI2C peripheral base pointers */
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#define LPI2C_BASE_PTRS IP_LPI2C_BASE_PTRS
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/** Interrupt vectors for the LPI2C peripheral type */
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#define LPI2C_IRQS { RTU_LPI2C1_IRQn, RTU_LPI2C2_IRQn }
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#endif /* _S32Z270_GLUE_MCUX_H_ */

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