arc64: Improve matching .f instructions

Author: Claudiu Zissulescu

gcc/config/arc64/arc64.md

@@ -1527,24 +1527,46 @@ vfins, vfsub, vfmul, vfdiv, vfrep, vpack, xbfu, xor, xorl"
    (set_attr "predicable" "no,no,yes,yes,no,yes,no,no,no")
    (set_attr "length" "*,*,4,4,4,4,4,8,8")])
 
-(define_insn "*cmpsi_zn"
+
+(define_insn "*cmp<mode>_ce"
+  [(cond_exec
+    (match_operator 2 "arc64_comparison_operator"
+		    [(match_operand 3 "cc_register" "") (const_int 0)])
+    (set (reg:CC CC_REGNUM)
+	 (compare:CC
+	  (match_operand:GPI 0 "nonmemory_operand" "r,    r,U06S0,S32S0,r")
+	  (match_operand:GPI 1 "nonmemory_operand" "r,U06S0,    r,    r,S32S0"))))]
+  "register_operand (operands[0], <MODE>mode)
+   || register_operand (operands[1], <MODE>mode)"
+  "@
+   cmp<sfxtab>.%m2\\t%0,%1
+   cmp<sfxtab>.%m2\\t%0,%1
+   rcmp<sfxtab>.%m2\\t%1,%0
+   rcmp<sfxtab>.%m2\\t%1,%0
+   cmp<sfxtab>.%m2\\t%0,%1"
+  [(set_attr "type" "cmp")
+   (set_attr "length" "4,4,4,8,8")])
+
+(define_insn "*cmp<mode>_zn"
   [(set (reg:CC_ZN CC_REGNUM)
-	(compare:CC_ZN (match_operand:SI 0 "register_operand" "q,r")
+	(compare:CC_ZN (match_operand:GPI 0 "register_operand" "q,r")
 		       (const_int 0)))]
   ""
-  "tst%?\\t%0,%0"
+  "tst<mcctab>%?\\t%0,%0"
   [(set_attr "type" "tst")
-   (set_attr "iscompact" "yes,no")
-   (set_attr "length" "2,4")])
+   (set_attr "iscompact" "maybe,no")
+   (set_attr "length" "*,4")])
 
-(define_insn "*cmpdi_zn"
-  [(set (reg:CC_ZN CC_REGNUM)
-	(compare:CC_ZN (match_operand:DI 0 "register_operand" "r")
-		       (const_int 0)))]
+(define_insn "*cmp<mode>_znce"
+  [(cond_exec
+    (match_operator 2 "arc64_comparison_operator"
+		    [(match_operand 1 "cc_register" "") (const_int 0)])
+   (set (reg:CC_ZN CC_REGNUM)
+	(compare:CC_ZN (match_operand:GPI 0 "register_operand" "r")
+		       (const_int 0))))]
   ""
-  "tstl\\t%0,%0"
+  "tst<mcctab>.%m2\\t%0,%0"
   [(set_attr "type" "tst")
-   (set_attr "iscompact" "no")
    (set_attr "length" "4")])
 
 (define_insn "fcmp<mode>"

gcc/config/arc64/arith.md

@@ -78,8 +78,36 @@
   [(set_attr "iscompact" "maybe,no,no,no,no,no")
    (set_attr "predicable" "no,yes,no,no,no,no")
    (set_attr "length"     "*,4,4,4,8,8")
-   (set_attr "type"       "<mntab>")]
-  )
+   (set_attr "type"       "<mntab>")])
+
+(define_insn "*<optab><mode>_cmp0"
+  [(set (reg:CC_ZN CC_REGNUM)
+	(compare:CC_ZN
+	 (ASHIFT:GPI
+	  (match_operand:GPI 1 "register_operand"  "     0,0")
+	  (match_operand:GPI 2 "nonmemory_operand" "rU06S0,S32S0"))
+	 (const_int 0)))
+    (set (match_operand:GPI 0 "register_operand"   "=     r,r")
+	 (ASHIFT:GPI (match_dup 1) (match_dup 2)))]
+  ""
+  "<mntab><sfxtab>.f\\t%0,%1,%2"
+  [(set_attr "iscompact" "no")
+   (set_attr "length"     "4,8")
+   (set_attr "type"       "<mntab>")])
+
+(define_insn "*<optab><mode>_cmp0_noout"
+  [(set (reg:CC_ZN CC_REGNUM)
+	(compare:CC_ZN
+	 (ASHIFT:GPI
+	  (match_operand:GPI 0 "register_operand"  "     r,r")
+	  (match_operand:GPI 1 "nonmemory_operand" "rU06S0,S32S0"))
+	 (const_int 0)))]
+  ""
+  "<mntab><sfxtab>.f\\t0,%0,%1"
+  [(set_attr "iscompact" "no")
+   (set_attr "length"     "4,8")
+   (set_attr "type"       "<mntab>")])
+
 
 (define_insn "*sub<mode>_insn"
   [(set (           match_operand:GPI 0 "register_operand"  "=q,    q,    q,     r,     r,    r,     r,    r,    r,    r,r")
@@ -164,6 +192,24 @@
    (set_attr "length"     "2,*,*,*,4,4,4,4,4,8")
    (set_attr "type"       "add")])
 
+;; This pattern is needed because the GT (pnz) is not reversible and I
+;; cannot convert CCmode to CC_ZNmode.
+(define_insn "*<ADDSUB:optab><GPI:mode>3_f"
+  [(set (reg:CC CC_REGNUM)
+	(compare:CC
+	 (ADDSUB:GPI
+	  (match_operand:GPI 1 "arc64_nonmem_operand" "0,    0,    0,    r,r,S32S0,    r")
+	  (match_operand:GPI 2 "arc64_nonmem_operand" "r,U06S0,S12S0,U06S0,r,    r,S32S0"))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand"      "=r,    r,    r,    r,r,    r,    r")
+	(ADDSUB:GPI (match_dup 1) (match_dup 2)))]
+  "register_operand (operands[1], <MODE>mode)
+   || register_operand (operands[2], <MODE>mode)"
+  "<ADDSUB:optab><GPI:sfxtab>.f\\t%0,%1,%2"
+  [(set_attr "predicable" "yes,yes,no,no,no,no,no")
+   (set_attr "length"     "4,4,4,4,4,8,8")
+   (set_attr "type"       "<ADDSUB:optab><GPI:sfxtab>")])
+
 ; Conditional execution
 (define_insn "*<optab><mode>_ce"
   [(cond_exec
@@ -315,6 +361,8 @@
    (set_attr "type"       "<mntab>")]
   )
 
+;; It may be worth to have a separate pattern for AND to take
+;; advantage of TST_S instruction.
 (define_insn "*<optab><mode>_cmp0_noout"
   [(set (reg:CC_ZN CC_REGNUM)
 	(compare:CC_ZN
@@ -462,6 +510,37 @@
    (set_attr "type"       "<optab><sfxtab>")]
   )
 
+(define_insn "*<optab><mode>3_cmp0"
+  [(set (reg:CC_ZN CC_REGNUM)
+	(compare:CC_ZN
+	 (DIVREM:GPI
+	  (match_operand:GPI 1 "arc64_nonmem_operand" " 0,r,S32S0,    r")
+	  (match_operand:GPI 2 "arc64_nonmem_operand" " r,r,    r,S32S0"))
+	(const_int 0)))
+   (set (match_operand:GPI 0 "register_operand"       "=r,r,    r,    r")
+	(DIVREM:GPI (match_dup 1)
+		    (match_dup 2)))]
+  "TARGET_ARC64_DIVREM
+   && (register_operand (operands[1], <MODE>mode)
+       || register_operand (operands[2], <MODE>mode))"
+  "<mntab><sfxtab>.f\\t%0,%1,%2"
+  [(set_attr "length"     "4,4,8,8")
+   (set_attr "type"       "<optab><sfxtab>")])
+
+(define_insn "*<optab><mode>3_cmp0_noout"
+  [(set (reg:CC_ZN CC_REGNUM)
+	(compare:CC_ZN
+	 (DIVREM:GPI
+	  (match_operand:GPI 0 "arc64_nonmem_operand" "r,S32S0,    r")
+	  (match_operand:GPI 1 "arc64_nonmem_operand" "r,    r,S32S0"))
+	(const_int 0)))]
+  "TARGET_ARC64_DIVREM
+   && (register_operand (operands[0], <MODE>mode)
+       || register_operand (operands[1], <MODE>mode))"
+  "<mntab><sfxtab>.f\\t0,%0,%1"
+  [(set_attr "length"     "4,8,8")
+   (set_attr "type"       "<optab><sfxtab>")])
+
 ;; To be merged into adddi3
 (define_insn "*add_tls_off"
   [(set (match_operand:DI 0 "register_operand" "=r")