@@ -1996,6 +1996,46 @@ vfins, vfsub, vfmul, vfdiv, vfrep, vpack, xbfu, xor, xorl"
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(set_attr "length" "8,8")
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(set_attr "predicable" "no")] )
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+ (define_insn "* extzvsi_cmp0"
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+ [ (set (reg: CC_ZN CC_REGNUM)
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+ (compare: CC_ZN
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+ (zero_extract: SI
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+ (match_operand: SI 1 "register_operand" "0,r")
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+ (match_operand 2 "const_int_operand" "n,n")
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+ (match_operand 3 "const_int_operand" "n,n"))
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+ (const_int 0)))
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+ (set (match_operand: SI 0 "register_operand" "=r,r")
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+ (zero_extract: SI (match_dup 1)
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+ (match_dup 2)
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+ (match_dup 3)))]
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+ ""
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+ {
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+ int assemble_op2 = (((INTVAL (operands[ 2] ) - 1) & 0x1f) << 5)
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+ | (INTVAL (operands[ 3] ) & 0x1f);
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+ operands[ 2] = GEN_INT (assemble_op2);
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+ return "xbfu.f\\ t%0,%1,%2";
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+ }
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+ [ (set_attr "type" "xbfu")
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+ (set_attr "length" "4,8")] )
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+
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+ (define_insn "* extzvsi_cmp0_noout"
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+ [ (set (reg: CC_ZN CC_REGNUM)
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+ (compare: CC_ZN
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+ (zero_extract: SI
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+ (match_operand: SI 0 "register_operand" "r")
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+ (match_operand 1 "const_int_operand" "n")
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+ (match_operand 2 "const_int_operand" "n"))
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+ (const_int 0)))]
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+ ""
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+ {
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+ int assemble_op2 = (((INTVAL (operands[ 1] ) - 1) & 0x1f) << 5)
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+ | (INTVAL (operands[ 2] ) & 0x1f);
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+ operands[ 2] = GEN_INT (assemble_op2);
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+ return "xbfu.f\\ t0,%1,%2";
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+ }
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+ [ (set_attr "type" "xbfu")
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+ (set_attr "length" "8")] )
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+
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;; -------------------------------------------------------------------
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;; Bitscan
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;; -------------------------------------------------------------------
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