arc64: Add BRcc combiner patterns

Author: Claudiu Zissulescu

gcc/config/arc64/arc64.c

@@ -1210,6 +1210,8 @@ get_arc64_condition_code (rtx comparison)
 {
   switch (GET_MODE (XEXP (comparison, 0)))
     {
+    case E_DImode: /* brcc/bbit instructions.  */
+    case E_SImode:
     case E_CCmode:
       switch (GET_CODE (comparison))
 	{
@@ -1236,8 +1238,6 @@ get_arc64_condition_code (rtx comparison)
 	default : gcc_unreachable ();
 	}
     case E_CC_Zmode:
-    case E_DImode: /* bbit instructions.  */
-    case E_SImode:
       switch (GET_CODE (comparison))
 	{
 	case EQ : return ARC_CC_EQ;

gcc/config/arc64/arc64.md

@@ -423,16 +423,17 @@
 
 (define_attr "type" "abs, adcl, add, addhl, addl, and, andl, asl,
 asll, asr, asrl, atldop, atldlop, bbit, bclr, bic, bl, block, bmsk,
-branch, branchcc, brk, bset, bsetl, btst, bxor, bxorl, cmp, dbnz, dmb,
-dmpywh, ex, div, divl, ext, fadd, fcmp, fsub, fmul, fdiv, fh2s, fmin,
-fmax, fsgnj, fsgnjx, fsgnjn, fmadd, fmov, fmsub, fnmadd, fnmsub,
-fsqrt, frnd, fs2d, fs2h, fd2s, int2fp, uint2fp, fp2int, fp2uint, ffs,
-fls, flag, jl, jump, ld, llock, lsr, lsrl, lr, max, maxl, min, minl,
-move, movecc, mod, modl, neg, nop, norm, normh, norml, mac, mpy, mpyl,
-not, notl, or, orl, return, ror, rol, sbcl, scond, setcc, sex, sr, st,
-sub, subl, swap, swapl, swape, swapel, sync, tst, trap, qmach, qmpyh,
-udiv, udivl, umod, umodl, unknown, vadd, vsub, vmac2h, vmpy2h, vfadd,
-vfext, vfins, vfsub, vfmul, vfdiv, vfrep, vpack, xbfu, xor, xorl"
+branch, brcc, branchcc, brk, bset, bsetl, btst, bxor, bxorl, cmp,
+dbnz, dmb, dmpywh, ex, div, divl, ext, fadd, fcmp, fsub, fmul, fdiv,
+fh2s, fmin, fmax, fsgnj, fsgnjx, fsgnjn, fmadd, fmov, fmsub, fnmadd,
+fnmsub, fsqrt, frnd, fs2d, fs2h, fd2s, int2fp, uint2fp, fp2int,
+fp2uint, ffs, fls, flag, jl, jump, ld, llock, lsr, lsrl, lr, max,
+maxl, min, minl, move, movecc, mod, modl, neg, nop, norm, normh,
+norml, mac, mpy, mpyl, not, notl, or, orl, return, ror, rol, sbcl,
+scond, setcc, sex, sr, st, sub, subl, swap, swapl, swape, swapel,
+sync, tst, trap, qmach, qmpyh, udiv, udivl, umod, umodl, unknown,
+vadd, vsub, vmac2h, vmpy2h, vfadd, vfext, vfins, vfsub, vfmul, vfdiv,
+vfrep, vpack, xbfu, xor, xorl"
   (const_string "unknown"))
 
 (define_attr "iscompact" "yes,no,maybe" (const_string "no"))
@@ -1410,6 +1411,47 @@ vfext, vfins, vfsub, vfmul, vfdiv, vfrep, vpack, xbfu, xor, xorl"
 	 (const_int 4)
 	 (const_int 8)))])
 
+;; combiner patterns for BRcc instructions.  We consider all BRcc
+;; supported comparisons but compare with zero. The positive range
+;; needs to take into account the limm size, and the pcl rounding.
+;; This pattern is under an option as it may prohibit further
+;; optimizations like if-conversion.
+(define_insn "*brcc"
+  [(set (pc)
+	(if_then_else
+	 (match_operator 3 "brcc_comparison_operator"
+			 [(match_operand:GPI 1 "register_operand"  "r,r")
+			  (match_operand:GPI 2 "brcc_2ndoperand" "U06S0r,U32S0")])
+	 (label_ref (match_operand 0 "" ""))
+	 (pc)))
+   (clobber (reg:CC_ZN CC_REGNUM))]
+  "!CROSSING_JUMP_P (insn) && TARGET_BRCC"
+  {
+   switch (get_attr_length (insn))
+     {
+     case 4:
+     case 8:
+       return \"br%m3<sfxtab>\\t%1,%2,%l0\";
+     default:
+       return \"cmp<sfxtab>\\t%1,%2\\n\\tb%m3\\t%l0\";
+     }
+  }
+  [(set_attr "type" "brcc")
+   (set (attr "length")
+	(cond [(and (ge (minus (match_dup 0) (pc)) (const_int -254))
+		    (le (minus (match_dup 0) (pc)) (const_int 248))
+		    (eq (symbol_ref "which_alternative") (const_int 0)))
+	       (const_int 4)
+	       (and (ge (minus (match_dup 0) (pc)) (const_int -254))
+		    (le (minus (match_dup 0) (pc)) (const_int 244))
+		    (eq (symbol_ref "which_alternative") (const_int 1)))
+	       (const_int 8)
+	       ;; This should be variable as well...
+	       (eq (symbol_ref "which_alternative") (const_int 0))
+	       (const_int 12)]
+	      (const_int 12)))
+   ])
+
 ;; -------------------------------------------------------------------
 ;; Sign/Zero extension
 ;; -------------------------------------------------------------------

gcc/config/arc64/arc64.opt

@@ -107,3 +107,7 @@ Enable wide floating point SIMD support.
 m128
 Target Report Mask(WIDE_LDST)
 Enable wide data transfer support.
+
+mbrcc
+Target Report Mask(BRCC)
+Generate BRcc instructions during combiner step.

gcc/config/arc64/predicates.md

@@ -208,3 +208,11 @@
 (define_predicate "bbitimm_operand"
   (and (match_code "const_int")
        (match_test "IS_POWEROF2_P (INTVAL (op))")))
+
+(define_special_predicate "brcc_comparison_operator"
+  (match_code "eq, ne, lt, ge, ltu, geu"))
+
+(define_predicate "brcc_2ndoperand"
+  (ior (match_operand 0 "register_operand")
+       (and (match_code "const_int")
+	    (match_test "INTVAL (op) != 0"))))