microblaze: Remove -Os shift optimizations that emits potentially dead code

Only applies to -Os. In picolibc testing it's found that this produces
code that compiler tries to squeeze into a single delay slot. And thus
only the first instruction emitted by this optimization is run and the rest
is skipped.

This partially reverts commit 104f6d7.

Signed-off-by: Alp Sayin <alpsayin@gmail.com>

Author: alpsayin

gcc/config/microblaze/microblaze.md

@@ -2051,27 +2051,6 @@ else
    (set_attr "length"	"8")]
 )
 
-(define_insn "*ashlsi3_with_size_opt"
-  [(set (match_operand:SI 0 "register_operand" "=&d")
-       (ashift:SI (match_operand:SI 1 "register_operand"  "d")
-                   (match_operand:SI 2 "immediate_operand" "I")))]
-  "(INTVAL (operands[2]) > 5 && optimize_size)"
-  {
-    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-
-    output_asm_insn ("ori\t%3,r0,%2", operands);
-    if (REGNO (operands[0]) != REGNO (operands[1]))
-        output_asm_insn ("addk\t%0,%1,r0", operands);
-
-    output_asm_insn ("addik\t%3,%3,-1", operands);
-    output_asm_insn ("bneid\t%3,.-4", operands);
-    return "addk\t%0,%0,%0";
-  }
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "SI")
-   (set_attr "length"  "20")]
-)
-
 (define_insn "*ashlsi3_with_rotate"
   [(set (match_operand:SI 0 "register_operand" "=&d")
        (ashift:SI (match_operand:SI 1 "register_operand"  "d")
@@ -2270,27 +2249,6 @@ else
   (set_attr "length"	"4,4")]
 )
 
-(define_insn "*ashrsi3_with_size_opt"
-  [(set (match_operand:SI 0 "register_operand" "=&d")
-       (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
-                   (match_operand:SI 2 "immediate_operand" "I")))]
-  "(INTVAL (operands[2]) > 5 && optimize_size)"
-  {
-    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-
-    output_asm_insn ("ori\t%3,r0,%2", operands);
-    if (REGNO (operands[0]) != REGNO (operands[1]))
-        output_asm_insn ("addk\t%0,%1,r0", operands);
-
-    output_asm_insn ("addik\t%3,%3,-1", operands);
-    output_asm_insn ("bneid\t%3,.-4", operands);
-    return "sra\t%0,%0";
-  }
-  [(set_attr "type"    "arith")
-  (set_attr "mode"    "SI")
-  (set_attr "length"  "20")]
-)
-
 (define_insn "*ashrsi_inline"
   [(set (match_operand:SI 0 "register_operand" "=&d")
        (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
@@ -2464,27 +2422,6 @@ else
   (set_attr "length"	"4,4")]
 )
 
-(define_insn "*lshrsi3_with_size_opt"
-  [(set (match_operand:SI 0 "register_operand" "=&d")
-       (lshiftrt:SI (match_operand:SI 1 "register_operand"  "d")
-                   (match_operand:SI 2 "immediate_operand" "I")))]
-  "(INTVAL (operands[2]) > 5 && optimize_size)"
-  {
-    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-
-    output_asm_insn ("ori\t%3,r0,%2", operands);
-    if (REGNO (operands[0]) != REGNO (operands[1]))
-        output_asm_insn ("addk\t%0,%1,r0", operands);
-
-    output_asm_insn ("addik\t%3,%3,-1", operands);
-    output_asm_insn ("bneid\t%3,.-4", operands);
-    return "srl\t%0,%0";
-  }
-  [(set_attr "type"    "multi")
-  (set_attr "mode"    "SI")
-  (set_attr "length"  "20")]
-)
-
 (define_insn "*lshrsi_inline"
   [(set (match_operand:SI 0 "register_operand" "=&d")
        (lshiftrt:SI (match_operand:SI 1 "register_operand"  "d")