arc64: Add BBIT[0/1][L] pattern

Author: Claudiu Zissulescu

gcc/config/arc64/arc64.c

@@ -1211,7 +1211,6 @@ get_arc64_condition_code (rtx comparison)
   switch (GET_MODE (XEXP (comparison, 0)))
     {
     case E_CCmode:
-    case E_SImode:
       switch (GET_CODE (comparison))
 	{
 	case EQ : return ARC_CC_EQ;
@@ -1237,6 +1236,8 @@ get_arc64_condition_code (rtx comparison)
 	default : gcc_unreachable ();
 	}
     case E_CC_Zmode:
+    case E_DImode: /* bbit instructions.  */
+    case E_SImode:
       switch (GET_CODE (comparison))
 	{
 	case EQ : return ARC_CC_EQ;
@@ -3499,29 +3500,32 @@ arc64_rtx_costs (rtx x, machine_mode mode, rtx_code outer,
 
     case CONST_INT:
       {
-	bool limm_p = true;
 	HOST_WIDE_INT imm = INTVAL (x);
 
 	/* In general any 32bit constant can be loaded immediately,
 	   however, when we compile for speed, we try to avoid
 	   them.  */
+	*cost = 0;
 	if (UNSIGNED_INT6 (imm))
-	  limm_p = false;
+	  return true;
 	else
 	  switch (outer)
 	    {
 	    case SET:
 	      if (SIGNED_INT12 (imm))
-		limm_p = false;
+		return true;
 	      break;
 
 	    default:
 	      break;
 	    }
-
-	*cost = limm_p ? cost_limm : 0;
-	return true;
       }
+      /* FALLTHRU */
+    case CONST:
+    case LABEL_REF:
+    case SYMBOL_REF:
+      *cost = cost_limm;
+      return true;
 
     case ASHIFT:
     case ASHIFTRT:
@@ -3540,6 +3544,18 @@ arc64_rtx_costs (rtx x, machine_mode mode, rtx_code outer,
       *cost = COSTS_N_INSNS (12);
       return true;
 
+    case EQ:
+    case NE:
+      if (outer == IF_THEN_ELSE
+	  && (GET_CODE (XEXP (x, 0)) == AND
+	      || GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT)
+	  && XEXP (x, 1) == const0_rtx)
+	{
+	  *cost = 0;
+	  return true;
+	}
+      break;
+
     default:
       break;
     }

gcc/config/arc64/arc64.h

@@ -457,6 +457,7 @@ extern const enum reg_class arc64_regno_to_regclass[];
 #define SIGNED_INT14_SHIFTED(X,S) (VERIFY_SHIFT(X,S) && SIGNED_INT12(X >> S))
 #define SIGNED_INT15_SHIFTED(X,S) (VERIFY_SHIFT(X,S) && SIGNED_INT12(X >> S))
 
+#define  IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X))
 
 /* These assume that REGNO is a hard or pseudo reg number.
    They give nonzero only if REGNO is a hard reg of the suitable class

gcc/config/arc64/arc64.md

@@ -422,17 +422,17 @@
 (define_attr "cost" "" (const_int 0))
 
 (define_attr "type" "abs, adcl, add, addhl, addl, and, andl, asl,
-asll, asr, asrl, atldop, atldlop, bclr, bic, bl, block, bmsk, branch,
-branchcc, brk, bset, bsetl, btst, bxor, bxorl, cmp, dbnz, dmb, dmpywh,
-ex, div, divl, ext, fadd, fcmp, fsub, fmul, fdiv, fh2s, fmin, fmax,
-fsgnj, fsgnjx, fsgnjn, fmadd, fmov, fmsub, fnmadd, fnmsub, fsqrt,
-frnd, fs2d, fs2h, fd2s, int2fp, uint2fp, fp2int, fp2uint, ffs, fls,
-flag, jl, jump, ld, llock, lsr, lsrl, lr, max, maxl, min, minl, move,
-movecc, mod, modl, neg, nop, norm, normh, norml, mac, mpy, mpyl, not,
-notl, or, orl, return, ror, rol, sbcl, scond, setcc, sex, sr, st, sub,
-subl, swap, swapl, swape, swapel, sync, tst, trap, qmach, qmpyh, udiv,
-udivl, umod, umodl, unknown, vadd, vsub, vmac2h, vmpy2h, vfadd, vfext,
-vfins, vfsub, vfmul, vfdiv, vfrep, vpack, xbfu, xor, xorl"
+asll, asr, asrl, atldop, atldlop, bbit, bclr, bic, bl, block, bmsk,
+branch, branchcc, brk, bset, bsetl, btst, bxor, bxorl, cmp, dbnz, dmb,
+dmpywh, ex, div, divl, ext, fadd, fcmp, fsub, fmul, fdiv, fh2s, fmin,
+fmax, fsgnj, fsgnjx, fsgnjn, fmadd, fmov, fmsub, fnmadd, fnmsub,
+fsqrt, frnd, fs2d, fs2h, fd2s, int2fp, uint2fp, fp2int, fp2uint, ffs,
+fls, flag, jl, jump, ld, llock, lsr, lsrl, lr, max, maxl, min, minl,
+move, movecc, mod, modl, neg, nop, norm, normh, norml, mac, mpy, mpyl,
+not, notl, or, orl, return, ror, rol, sbcl, scond, setcc, sex, sr, st,
+sub, subl, swap, swapl, swape, swapel, sync, tst, trap, qmach, qmpyh,
+udiv, udivl, umod, umodl, unknown, vadd, vsub, vmac2h, vmpy2h, vfadd,
+vfext, vfins, vfsub, vfmul, vfdiv, vfrep, vpack, xbfu, xor, xorl"
   (const_string "unknown"))
 
 (define_attr "iscompact" "yes,no,maybe" (const_string "no"))
@@ -1345,6 +1345,71 @@ vfins, vfsub, vfmul, vfdiv, vfrep, vpack, xbfu, xor, xorl"
   [(set_attr "type" "jump")
    (set_attr "length" "2,4")])
 
+;; combiner patterns used to match bbit0/1 instructions.
+;; Unfortunately, I cannot use splitting for this pattern as the
+;; insn length is know very late during compilation process.
+(define_insn "*bbit_and"
+  [(set (pc)
+	(if_then_else
+	 (match_operator 3 "equality_comparison_operator"
+			 [(and:GPI
+			   (match_operand:GPI 1 "register_operand" "r")
+			   (match_operand 2 "bbitimm_operand" ""))
+			  (const_int 0)])
+	 (label_ref (match_operand 0 "" ""))
+	 (pc)))
+   (clobber (reg:CC_ZN CC_REGNUM))]
+  "!CROSSING_JUMP_P (insn)"
+  {
+   operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
+   switch (get_attr_length (insn))
+     {
+     case 4:
+       return (GET_CODE (operands[3]) == EQ
+	       ? \"bbit0<sfxtab>\\t%1,%2,%l0\" : \"bbit1<sfxtab>\\t%1,%2,%l0\");
+     default:
+       return \"btst<sfxtab>\\t%1,%2\\n\\tb%m3\\t%l0\";
+     }
+  }
+  [(set_attr "type" "bbit")
+   (set (attr "length")
+	(if_then_else
+	 (and (ge (minus (match_dup 0) (pc)) (const_int -254))
+	      (le (minus (match_dup 0) (pc)) (const_int 250)))
+	 (const_int 4)
+	 (const_int 8)))])
+
+(define_insn "*bbit_zext"
+  [(set (pc)
+	(if_then_else
+	 (match_operator 3 "equality_comparison_operator"
+			 [(zero_extract:GPI
+			   (match_operand:GPI 1 "register_operand" "r")
+			   (const_int 1)
+			   (match_operand:GPI 2 "nonmemory_operand" "ir"))
+			  (const_int 0)])
+	 (label_ref (match_operand 0 "" ""))
+	 (pc)))
+   (clobber (reg:CC_ZN CC_REGNUM))]
+  "!CROSSING_JUMP_P (insn)"
+  {
+   switch (get_attr_length (insn))
+     {
+     case 4:
+       return (GET_CODE (operands[3]) == EQ
+	       ? \"bbit0<sfxtab>\\t%1,%2,%l0\" : \"bbit1<sfxtab>\\t%1,%2,%l0\");
+     default:
+       return \"btst<sfxtab>\\t%1,%2\\n\\tb%m3\\t%l0\";
+     }
+  }
+  [(set_attr "type" "bbit")
+   (set (attr "length")
+	(if_then_else
+	 (and (ge (minus (match_dup 0) (pc)) (const_int -254))
+	      (le (minus (match_dup 0) (pc)) (const_int 250)))
+	 (const_int 4)
+	 (const_int 8)))])
+
 ;; -------------------------------------------------------------------
 ;; Sign/Zero extension
 ;; -------------------------------------------------------------------

gcc/config/arc64/predicates.md

@@ -204,3 +204,7 @@
 (define_predicate "unsign_immediate_operand"
   (and (match_code "const_int")
        (match_test "UNSIGNED_INT16 (INTVAL (op))")))
+
+(define_predicate "bbitimm_operand"
+  (and (match_code "const_int")
+       (match_test "IS_POWEROF2_P (INTVAL (op))")))