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Description
The roughly flows for my PIO application are described as below
- Pull data from CPU
- Wait expected signal <- Which I need to simulate in Typescript
- Write data to ISR (input shift register) and trigger DMA if FIFO is full.
Since CPU, DMA, PIO and timers all execute in single thread, it's hard to simulate the signal with expected timing.
When PIO is running and waiting for data from CPU, but meanwhile CPU is not running (the only thread is occupied by PIO).
Similar situation for PIO waiting for DMA execution.
Any idea to this problem?
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