fix(pio): incorrect FDEBUG TXSTALL/RXSTALL behavior

Writing to FDEBUG clears the TXSTALL/RXSTALL, even if the FIFOs are still empty/full (respectively), which is not the correct behavior.

Author: urish

src/peripherals/pio.spec.ts

@@ -56,6 +56,7 @@ const SM0_PINCTRL = 0x502000dc;
 const SM2_INSTR = 0x50200108;
 const INTR = 0x50200128;
 const IRQ0_INTE = 0x5020012c;
+const FDEBUG = 0x50200008; // Debug register
 
 const NVIC_ISPR = 0xe000e200;
 const NVIC_ICPR = 0xe000e280;
@@ -85,6 +86,9 @@ const EXECCTRL_WRAP_BOTTOM_SHIFT = 7;
 const EXECCTRL_WRAP_TOP_SHIFT = 12;
 const EXECCTRL_STATUS_N_SHIFT = 0;
 
+// FDEBUG bits
+const FDEBUG_TXSTALL = 1 << 24;
+
 const DBG_PADOUT = 0x5020003c;
 
 const SET_COUNT_SHIFT = 26;
@@ -559,6 +563,38 @@ describe('PIO', () => {
     expect((await cpu.readUint32(NVIC_ISPR)) & PIO_IRQ0).toEqual(PIO_IRQ0);
   });
 
+  it('should set TXSTALL flag in FDEBUG when trying to pull from an empty TX FIFO and only clear it after TX is no longer stalled', async () => {
+    await resetStateMachines();
+
+    // Clear FDEBUG register
+    await cpu.writeUint32(FDEBUG, 0xffffffff);
+    expect(await cpu.readUint32(FDEBUG)).toBe(0);
+
+    // Make sure TX FIFO is empty
+    expect(await cpu.readUint32(FLEVEL)).toEqual(0 << TX0_SHIFT);
+
+    // Attempt to pull from an empty TX FIFO
+    await cpu.writeUint32(SM0_INSTR, pioPULL(false, false));
+
+    // Check that the TXSTALL flag is set
+    expect((await cpu.readUint32(FDEBUG)) & (FDEBUG_TXSTALL << 0)).toEqual(FDEBUG_TXSTALL << 0);
+
+    // Try clearing the TXSTALL flag while TX FIFO is still empty
+    await cpu.writeUint32(FDEBUG, FDEBUG_TXSTALL << 0);
+
+    // Verify the flag is NOT cleared because TX is still stalled
+    expect((await cpu.readUint32(FDEBUG)) & (FDEBUG_TXSTALL << 0)).toEqual(FDEBUG_TXSTALL << 0);
+
+    // Push something to TX FIFO to unstall it
+    await cpu.writeUint32(TXF0, 42);
+
+    // Now try clearing the flag again
+    await cpu.writeUint32(FDEBUG, FDEBUG_TXSTALL << 0);
+
+    // Now the flag should be cleared
+    expect((await cpu.readUint32(FDEBUG)) & (FDEBUG_TXSTALL << 0)).toEqual(0);
+  });
+
   it('should update RXFNEMPTY flag in INTR according to the level of the RX FIFO (issue #73)', async () => {
     await resetStateMachines();
     await cpu.writeUint32(IRQ0_INTE, INTR_SM0_RXNEMPTY);

src/peripherals/pio.ts

@@ -187,6 +187,7 @@ export class StateMachine {
       return;
     }
     this.txFIFO.push(value);
+    this.pio.txStall &= ~(FDEBUG_TXSTALL << this.index);
     this.updateDMATx();
     this.checkWait();
     if (this.txFIFO.full) {
@@ -200,6 +201,7 @@ export class StateMachine {
       return 0;
     }
     const result = this.rxFIFO.pull();
+    this.pio.rxStall &= ~(FDEBUG_RXSTALL << this.index);
     this.updateDMARx();
     this.checkWait();
     if (this.rxFIFO.empty) {
@@ -504,7 +506,8 @@ export class StateMachine {
             this.updateDMARx();
             this.pio.checkInterrupts();
           } else {
-            this.pio.fdebug |= FDEBUG_RXSTALL << this.index;
+            this.pio.rxStall |= FDEBUG_RXSTALL << this.index;
+            this.pio.fdebug |= this.pio.rxStall;
             this.wait(WaitType.rxFIFO, false, this.inputShiftReg);
           }
           this.inputShiftCount = 0;
@@ -523,7 +526,8 @@ export class StateMachine {
             this.updateDMATx();
             this.pio.checkInterrupts();
           } else {
-            this.pio.fdebug |= FDEBUG_TXSTALL << this.index;
+            this.pio.txStall |= FDEBUG_TXSTALL << this.index;
+            this.pio.fdebug |= this.pio.txStall;
             this.wait(WaitType.Out, false, arg);
           }
         }
@@ -556,7 +560,8 @@ export class StateMachine {
             this.updateDMATx();
             this.pio.checkInterrupts();
           } else {
-            this.pio.fdebug |= FDEBUG_TXSTALL << this.index;
+            this.pio.txStall |= FDEBUG_TXSTALL << this.index;
+            this.pio.fdebug |= this.pio.txStall;
             if (block) {
               this.wait(WaitType.txFIFO, false, 0);
             } else {
@@ -578,7 +583,8 @@ export class StateMachine {
             this.updateDMARx();
             this.pio.checkInterrupts();
           } else {
-            this.pio.fdebug |= FDEBUG_RXSTALL << this.index;
+            this.pio.rxStall |= FDEBUG_RXSTALL << this.index;
+            this.pio.fdebug |= this.pio.rxStall;
             if (block) {
               this.wait(WaitType.rxFIFO, false, this.inputShiftReg);
             }
@@ -928,6 +934,8 @@ export class RPPIO extends BasePeripheral implements Peripheral {
 
   stopped = true;
   fdebug = 0;
+  txStall = 0;
+  rxStall = 0;
   inputSyncBypass = 0;
   irq = 0;
   pinValues = 0;
@@ -1098,6 +1106,7 @@ export class RPPIO extends BasePeripheral implements Peripheral {
       }
       case FDEBUG:
         this.fdebug &= ~this.rawWriteValue;
+        this.fdebug |= this.txStall | this.rxStall;
         break;
       case TXF0:
         this.machines[0].writeFIFO(value);