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c1570c1570
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fix(core): ARM cycle counting (#119)
add APB penalty, add missing LDR penalties Co-authored-by: c1570 <c1570@users.noreply.github.com>
1 parent 1c85e38 commit 1e3a877

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2 files changed

+27
-45
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2 files changed

+27
-45
lines changed

‎src/cortex-m0-core.ts

Lines changed: 26 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
import { MAX_HARDWARE_IRQ } from './irq';
2-
import { RP2040, SIO_START_ADDRESS } from './rp2040';
2+
import { RP2040, APB_START_ADDRESS, SIO_START_ADDRESS } from './rp2040';
33

44
/* eslint-disable @typescript-eslint/no-unused-vars */
55
const EXC_RESET = 1;
@@ -568,9 +568,15 @@ export class CortexM0Core {
568568
return result & 0xffffffff;
569569
}
570570

571-
slowIO(addr: number) {
571+
cyclesIO(addr: number, write = false) {
572572
addr = addr >>> 0;
573-
return addr < SIO_START_ADDRESS || addr > SIO_START_ADDRESS + 0x10000000;
573+
if(addr >= SIO_START_ADDRESS && addr < SIO_START_ADDRESS + 0x10000000) {
574+
return 0;
575+
}
576+
if(addr >= APB_START_ADDRESS && addr < APB_START_ADDRESS + 0x10000000) {
577+
return write ? 4 : 3;
578+
}
579+
return 1;
574580
}
575581

576582
executeInstruction() {
@@ -828,13 +834,15 @@ export class CortexM0Core {
828834
const Rn = (opcode >> 3) & 0x7;
829835
const Rt = opcode & 0x7;
830836
const addr = this.registers[Rn] + imm5;
837+
this.cycles += this.cyclesIO(addr);
831838
this.registers[Rt] = this.readUint32(addr);
832839
}
833840
// LDR (sp + immediate)
834841
else if (opcode >> 11 === 0b10011) {
835842
const Rt = (opcode >> 8) & 0x7;
836843
const imm8 = opcode & 0xff;
837844
const addr = this.SP + (imm8 << 2);
845+
this.cycles += this.cyclesIO(addr);
838846
this.registers[Rt] = this.readUint32(addr);
839847
}
840848
// LDR (literal)
@@ -843,6 +851,7 @@ export class CortexM0Core {
843851
const Rt = (opcode >> 8) & 7;
844852
const nextPC = this.PC + 2;
845853
const addr = (nextPC & 0xfffffffc) + imm8;
854+
this.cycles += this.cyclesIO(addr);
846855
this.registers[Rt] = this.readUint32(addr);
847856
}
848857
// LDR (register)
@@ -851,9 +860,7 @@ export class CortexM0Core {
851860
const Rn = (opcode >> 3) & 0x7;
852861
const Rt = opcode & 0x7;
853862
const addr = this.registers[Rm] + this.registers[Rn];
854-
if (this.slowIO(addr)) {
855-
this.cycles++;
856-
}
863+
this.cycles += this.cyclesIO(addr);
857864
this.registers[Rt] = this.readUint32(addr);
858865
}
859866
// LDRB (immediate)
@@ -862,9 +869,7 @@ export class CortexM0Core {
862869
const Rn = (opcode >> 3) & 0x7;
863870
const Rt = opcode & 0x7;
864871
const addr = this.registers[Rn] + imm5;
865-
if (this.slowIO(addr)) {
866-
this.cycles++;
867-
}
872+
this.cycles += this.cyclesIO(addr);
868873
this.registers[Rt] = this.readUint8(addr);
869874
}
870875
// LDRB (register)
@@ -873,9 +878,7 @@ export class CortexM0Core {
873878
const Rn = (opcode >> 3) & 0x7;
874879
const Rt = opcode & 0x7;
875880
const addr = this.registers[Rm] + this.registers[Rn];
876-
if (this.slowIO(addr)) {
877-
this.cycles++;
878-
}
881+
this.cycles += this.cyclesIO(addr);
879882
this.registers[Rt] = this.readUint8(addr);
880883
}
881884
// LDRH (immediate)
@@ -884,9 +887,7 @@ export class CortexM0Core {
884887
const Rn = (opcode >> 3) & 0x7;
885888
const Rt = opcode & 0x7;
886889
const addr = this.registers[Rn] + (imm5 << 1);
887-
if (this.slowIO(addr)) {
888-
this.cycles++;
889-
}
890+
this.cycles += this.cyclesIO(addr);
890891
this.registers[Rt] = this.readUint16(addr);
891892
}
892893
// LDRH (register)
@@ -895,9 +896,7 @@ export class CortexM0Core {
895896
const Rn = (opcode >> 3) & 0x7;
896897
const Rt = opcode & 0x7;
897898
const addr = this.registers[Rm] + this.registers[Rn];
898-
if (this.slowIO(addr)) {
899-
this.cycles++;
900-
}
899+
this.cycles += this.cyclesIO(addr);
901900
this.registers[Rt] = this.readUint16(addr);
902901
}
903902
// LDRSB
@@ -906,9 +905,7 @@ export class CortexM0Core {
906905
const Rn = (opcode >> 3) & 0x7;
907906
const Rt = opcode & 0x7;
908907
const addr = this.registers[Rm] + this.registers[Rn];
909-
if (this.slowIO(addr)) {
910-
this.cycles++;
911-
}
908+
this.cycles += this.cyclesIO(addr);
912909
this.registers[Rt] = signExtend8(this.readUint8(addr));
913910
}
914911
// LDRSH
@@ -917,9 +914,7 @@ export class CortexM0Core {
917914
const Rn = (opcode >> 3) & 0x7;
918915
const Rt = opcode & 0x7;
919916
const addr = this.registers[Rm] + this.registers[Rn];
920-
if (this.slowIO(addr)) {
921-
this.cycles++;
922-
}
917+
this.cycles += this.cyclesIO(addr);
923918
this.registers[Rt] = signExtend16(this.readUint16(addr));
924919
}
925920
// LSLS (immediate)
@@ -1161,19 +1156,15 @@ export class CortexM0Core {
11611156
const Rn = (opcode >> 3) & 0x7;
11621157
const Rt = opcode & 0x7;
11631158
const address = this.registers[Rn] + imm5;
1164-
if (this.slowIO(address)) {
1165-
this.cycles++;
1166-
}
1159+
this.cycles += this.cyclesIO(address, true);
11671160
this.writeUint32(address, this.registers[Rt]);
11681161
}
11691162
// STR (sp + immediate)
11701163
else if (opcode >> 11 === 0b10010) {
11711164
const Rt = (opcode >> 8) & 0x7;
11721165
const imm8 = opcode & 0xff;
11731166
const address = this.SP + (imm8 << 2);
1174-
if (this.slowIO(address)) {
1175-
this.cycles++;
1176-
}
1167+
this.cycles += this.cyclesIO(address, true);
11771168
this.writeUint32(address, this.registers[Rt]);
11781169
}
11791170
// STR (register)
@@ -1182,9 +1173,7 @@ export class CortexM0Core {
11821173
const Rn = (opcode >> 3) & 0x7;
11831174
const Rt = opcode & 0x7;
11841175
const address = this.registers[Rm] + this.registers[Rn];
1185-
if (this.slowIO(address)) {
1186-
this.cycles++;
1187-
}
1176+
this.cycles += this.cyclesIO(address, true);
11881177
this.writeUint32(address, this.registers[Rt]);
11891178
}
11901179
// STRB (immediate)
@@ -1193,9 +1182,7 @@ export class CortexM0Core {
11931182
const Rn = (opcode >> 3) & 0x7;
11941183
const Rt = opcode & 0x7;
11951184
const address = this.registers[Rn] + imm5;
1196-
if (this.slowIO(address)) {
1197-
this.cycles++;
1198-
}
1185+
this.cycles += this.cyclesIO(address, true);
11991186
this.writeUint8(address, this.registers[Rt]);
12001187
}
12011188
// STRB (register)
@@ -1204,9 +1191,7 @@ export class CortexM0Core {
12041191
const Rn = (opcode >> 3) & 0x7;
12051192
const Rt = opcode & 0x7;
12061193
const address = this.registers[Rm] + this.registers[Rn];
1207-
if (this.slowIO(address)) {
1208-
this.cycles++;
1209-
}
1194+
this.cycles += this.cyclesIO(address, true);
12101195
this.writeUint8(address, this.registers[Rt]);
12111196
}
12121197
// STRH (immediate)
@@ -1215,9 +1200,7 @@ export class CortexM0Core {
12151200
const Rn = (opcode >> 3) & 0x7;
12161201
const Rt = opcode & 0x7;
12171202
const address = this.registers[Rn] + imm5;
1218-
if (this.slowIO(address)) {
1219-
this.cycles++;
1220-
}
1203+
this.cycles += this.cyclesIO(address, true);
12211204
this.writeUint16(address, this.registers[Rt]);
12221205
}
12231206
// STRH (register)
@@ -1226,9 +1209,7 @@ export class CortexM0Core {
12261209
const Rn = (opcode >> 3) & 0x7;
12271210
const Rt = opcode & 0x7;
12281211
const address = this.registers[Rm] + this.registers[Rn];
1229-
if (this.slowIO(address)) {
1230-
this.cycles++;
1231-
}
1212+
this.cycles += this.cyclesIO(address, true);
12321213
this.writeUint16(address, this.registers[Rt]);
12331214
}
12341215
// SUB (SP minus immediate)

‎src/rp2040.ts

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ import { RPTBMAN } from './peripherals/tbman';
2828

2929
export const FLASH_START_ADDRESS = 0x10000000;
3030
export const RAM_START_ADDRESS = 0x20000000;
31+
export const APB_START_ADDRESS = 0x40000000;
3132
export const DPRAM_START_ADDRESS = 0x50100000;
3233
export const SIO_START_ADDRESS = 0xd0000000;
3334

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