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tests: convert to async simulator syntax.
This causes one test to fail due to a now-exposed bug. Co-authored-by: Wanda <wanda-phi@users.noreply.github.com>
1 parent 7cabe35 commit e24b9b4

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6 files changed

+453
-466
lines changed

6 files changed

+453
-466
lines changed

‎tests/test_lib_cdc.py

Lines changed: 101 additions & 108 deletions
Original file line numberDiff line numberDiff line change
@@ -23,16 +23,14 @@ def test_basic(self):
2323

2424
sim = Simulator(frag)
2525
sim.add_clock(1e-6)
26-
def process():
27-
self.assertEqual((yield o), 0)
28-
yield i.eq(1)
29-
yield Tick()
30-
self.assertEqual((yield o), 0)
31-
yield Tick()
32-
self.assertEqual((yield o), 0)
33-
yield Tick()
34-
self.assertEqual((yield o), 1)
35-
sim.add_process(process)
26+
async def testbench(ctx):
27+
self.assertEqual(ctx.get(o), 0)
28+
ctx.set(i, 1)
29+
await ctx.tick()
30+
self.assertEqual(ctx.get(o), 0)
31+
await ctx.tick()
32+
self.assertEqual(ctx.get(o), 1)
33+
sim.add_testbench(testbench)
3634
sim.run()
3735

3836
def test_init_value(self):
@@ -42,16 +40,14 @@ def test_init_value(self):
4240

4341
sim = Simulator(frag)
4442
sim.add_clock(1e-6)
45-
def process():
46-
self.assertEqual((yield o), 1)
47-
yield i.eq(0)
48-
yield Tick()
49-
self.assertEqual((yield o), 1)
50-
yield Tick()
51-
self.assertEqual((yield o), 1)
52-
yield Tick()
53-
self.assertEqual((yield o), 0)
54-
sim.add_process(process)
43+
async def testbench(ctx):
44+
self.assertEqual(ctx.get(o), 1)
45+
ctx.set(i, 0)
46+
await ctx.tick()
47+
self.assertEqual(ctx.get(o), 1)
48+
await ctx.tick()
49+
self.assertEqual(ctx.get(o), 0)
50+
sim.add_testbench(testbench)
5551
sim.run()
5652

5753
def test_reset_value(self):
@@ -63,16 +59,14 @@ def test_reset_value(self):
6359

6460
sim = Simulator(frag)
6561
sim.add_clock(1e-6)
66-
def process():
67-
self.assertEqual((yield o), 1)
68-
yield i.eq(0)
69-
yield Tick()
70-
self.assertEqual((yield o), 1)
71-
yield Tick()
72-
self.assertEqual((yield o), 1)
73-
yield Tick()
74-
self.assertEqual((yield o), 0)
75-
sim.add_process(process)
62+
async def testbench(ctx):
63+
self.assertEqual(ctx.get(o), 1)
64+
ctx.set(i, 0)
65+
await ctx.tick()
66+
self.assertEqual(ctx.get(o), 1)
67+
await ctx.tick()
68+
self.assertEqual(ctx.get(o), 0)
69+
sim.add_testbench(testbench)
7670
sim.run()
7771

7872
def test_reset_wrong(self):
@@ -114,31 +108,31 @@ def test_pos_edge(self):
114108

115109
sim = Simulator(m)
116110
sim.add_clock(1e-6)
117-
def process():
111+
async def testbench(ctx):
118112
# initial reset
119-
self.assertEqual((yield i), 0)
120-
self.assertEqual((yield o), 1)
121-
yield Tick()
122-
self.assertEqual((yield o), 1)
123-
yield Tick()
124-
self.assertEqual((yield o), 0)
125-
yield Tick()
126-
self.assertEqual((yield o), 0)
127-
yield Tick()
113+
self.assertEqual(ctx.get(i), 0)
114+
self.assertEqual(ctx.get(o), 1)
115+
await ctx.tick()
116+
self.assertEqual(ctx.get(o), 1)
117+
await ctx.tick()
118+
self.assertEqual(ctx.get(o), 0)
119+
await ctx.tick()
120+
self.assertEqual(ctx.get(o), 0)
121+
await ctx.tick()
128122

129-
yield i.eq(1)
130-
self.assertEqual((yield o), 1)
131-
yield Tick()
132-
self.assertEqual((yield o), 1)
133-
yield i.eq(0)
134-
yield Tick()
135-
self.assertEqual((yield o), 1)
136-
yield Tick()
137-
self.assertEqual((yield o), 0)
138-
yield Tick()
139-
self.assertEqual((yield o), 0)
140-
yield Tick()
141-
sim.add_testbench(process)
123+
ctx.set(i, 1)
124+
self.assertEqual(ctx.get(o), 1)
125+
await ctx.tick()
126+
self.assertEqual(ctx.get(o), 1)
127+
ctx.set(i, 0)
128+
await ctx.tick()
129+
self.assertEqual(ctx.get(o), 1)
130+
await ctx.tick()
131+
self.assertEqual(ctx.get(o), 0)
132+
await ctx.tick()
133+
self.assertEqual(ctx.get(o), 0)
134+
await ctx.tick()
135+
sim.add_testbench(testbench)
142136
with sim.write_vcd("test.vcd"):
143137
sim.run()
144138

@@ -151,31 +145,31 @@ def test_neg_edge(self):
151145

152146
sim = Simulator(m)
153147
sim.add_clock(1e-6)
154-
def process():
148+
async def testbench(ctx):
155149
# initial reset
156-
self.assertEqual((yield i), 1)
157-
self.assertEqual((yield o), 1)
158-
yield Tick()
159-
self.assertEqual((yield o), 1)
160-
yield Tick()
161-
self.assertEqual((yield o), 0)
162-
yield Tick()
163-
self.assertEqual((yield o), 0)
164-
yield Tick()
150+
self.assertEqual(ctx.get(i), 1)
151+
self.assertEqual(ctx.get(o), 1)
152+
await ctx.tick()
153+
self.assertEqual(ctx.get(o), 1)
154+
await ctx.tick()
155+
self.assertEqual(ctx.get(o), 0)
156+
await ctx.tick()
157+
self.assertEqual(ctx.get(o), 0)
158+
await ctx.tick()
165159

166-
yield i.eq(0)
167-
self.assertEqual((yield o), 1)
168-
yield Tick()
169-
self.assertEqual((yield o), 1)
170-
yield i.eq(1)
171-
yield Tick()
172-
self.assertEqual((yield o), 1)
173-
yield Tick()
174-
self.assertEqual((yield o), 0)
175-
yield Tick()
176-
self.assertEqual((yield o), 0)
177-
yield Tick()
178-
sim.add_testbench(process)
160+
ctx.set(i, 0)
161+
self.assertEqual(ctx.get(o), 1)
162+
await ctx.tick()
163+
self.assertEqual(ctx.get(o), 1)
164+
ctx.set(i, 1)
165+
await ctx.tick()
166+
self.assertEqual(ctx.get(o), 1)
167+
await ctx.tick()
168+
self.assertEqual(ctx.get(o), 0)
169+
await ctx.tick()
170+
self.assertEqual(ctx.get(o), 0)
171+
await ctx.tick()
172+
sim.add_testbench(testbench)
179173
with sim.write_vcd("test.vcd"):
180174
sim.run()
181175

@@ -199,31 +193,30 @@ def test_basic(self):
199193

200194
sim = Simulator(m)
201195
sim.add_clock(1e-6)
202-
def process():
196+
async def testbench(ctx):
203197
# initial reset
204-
self.assertEqual((yield s), 1)
205-
yield Tick()
206-
self.assertEqual((yield s), 1)
207-
yield Tick()
208-
self.assertEqual((yield s), 1)
209-
yield Tick()
210-
self.assertEqual((yield s), 0)
211-
yield Tick()
198+
self.assertEqual(ctx.get(s), 1)
199+
await ctx.tick()
200+
self.assertEqual(ctx.get(s), 1)
201+
await ctx.tick()
202+
self.assertEqual(ctx.get(s), 1)
203+
await ctx.tick()
204+
self.assertEqual(ctx.get(s), 0)
205+
await ctx.tick()
212206

213-
yield arst.eq(1)
214-
yield Delay(1e-8)
215-
self.assertEqual((yield s), 0)
216-
yield Tick()
217-
self.assertEqual((yield s), 1)
218-
yield arst.eq(0)
219-
yield Tick()
220-
self.assertEqual((yield s), 1)
221-
yield Tick()
222-
self.assertEqual((yield s), 1)
223-
yield Tick()
224-
self.assertEqual((yield s), 0)
225-
yield Tick()
226-
sim.add_testbench(process)
207+
ctx.set(arst, 1)
208+
self.assertEqual(ctx.get(s), 0)
209+
await ctx.tick()
210+
self.assertEqual(ctx.get(s), 1)
211+
ctx.set(arst, 0)
212+
await ctx.tick()
213+
self.assertEqual(ctx.get(s), 1)
214+
await ctx.tick()
215+
self.assertEqual(ctx.get(s), 1)
216+
await ctx.tick()
217+
self.assertEqual(ctx.get(s), 0)
218+
await ctx.tick()
219+
sim.add_testbench(testbench)
227220
with sim.write_vcd("test.vcd"):
228221
sim.run()
229222

@@ -245,21 +238,21 @@ def test_smoke(self):
245238

246239
sim = Simulator(m)
247240
sim.add_clock(1e-6)
248-
def process():
249-
yield ps.i.eq(0)
241+
async def testbench(ctx):
242+
ctx.set(ps.i, 0)
250243
# TODO: think about reset
251244
for n in range(5):
252-
yield Tick()
245+
await ctx.tick()
253246
# Make sure no pulses are generated in quiescent state
254247
for n in range(3):
255-
yield Tick()
256-
self.assertEqual((yield ps.o), 0)
248+
await ctx.tick()
249+
self.assertEqual(ctx.get(ps.o), 0)
257250
# Check conservation of pulses
258251
accum = 0
259252
for n in range(10):
260-
yield ps.i.eq(1 if n < 4 else 0)
261-
yield Tick()
262-
accum += yield ps.o
253+
ctx.set(ps.i, 1 if n < 4 else 0)
254+
await ctx.tick()
255+
accum += ctx.get(ps.o)
263256
self.assertEqual(accum, 4)
264-
sim.add_process(process)
257+
sim.add_testbench(testbench)
265258
sim.run()

‎tests/test_lib_coding.py

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -12,68 +12,68 @@
1212
class EncoderTestCase(FHDLTestCase):
1313
def test_basic(self):
1414
enc = Encoder(4)
15-
def process():
16-
self.assertEqual((yield enc.n), 1)
17-
self.assertEqual((yield enc.o), 0)
15+
async def testbench(ctx):
16+
self.assertEqual(ctx.get(enc.n), 1)
17+
self.assertEqual(ctx.get(enc.o), 0)
1818

19-
yield enc.i.eq(0b0001)
20-
self.assertEqual((yield enc.n), 0)
21-
self.assertEqual((yield enc.o), 0)
19+
ctx.set(enc.i, 0b0001)
20+
self.assertEqual(ctx.get(enc.n), 0)
21+
self.assertEqual(ctx.get(enc.o), 0)
2222

23-
yield enc.i.eq(0b0100)
24-
self.assertEqual((yield enc.n), 0)
25-
self.assertEqual((yield enc.o), 2)
23+
ctx.set(enc.i, 0b0100)
24+
self.assertEqual(ctx.get(enc.n), 0)
25+
self.assertEqual(ctx.get(enc.o), 2)
2626

27-
yield enc.i.eq(0b0110)
28-
self.assertEqual((yield enc.n), 1)
29-
self.assertEqual((yield enc.o), 0)
27+
ctx.set(enc.i, 0b0110)
28+
self.assertEqual(ctx.get(enc.n), 1)
29+
self.assertEqual(ctx.get(enc.o), 0)
3030

3131
sim = Simulator(enc)
32-
sim.add_testbench(process)
32+
sim.add_testbench(testbench)
3333
sim.run()
3434

3535

3636
class PriorityEncoderTestCase(FHDLTestCase):
3737
def test_basic(self):
3838
enc = PriorityEncoder(4)
39-
def process():
40-
self.assertEqual((yield enc.n), 1)
41-
self.assertEqual((yield enc.o), 0)
39+
async def testbench(ctx):
40+
self.assertEqual(ctx.get(enc.n), 1)
41+
self.assertEqual(ctx.get(enc.o), 0)
4242

43-
yield enc.i.eq(0b0001)
44-
self.assertEqual((yield enc.n), 0)
45-
self.assertEqual((yield enc.o), 0)
43+
ctx.set(enc.i, 0b0001)
44+
self.assertEqual(ctx.get(enc.n), 0)
45+
self.assertEqual(ctx.get(enc.o), 0)
4646

47-
yield enc.i.eq(0b0100)
48-
self.assertEqual((yield enc.n), 0)
49-
self.assertEqual((yield enc.o), 2)
47+
ctx.set(enc.i, 0b0100)
48+
self.assertEqual(ctx.get(enc.n), 0)
49+
self.assertEqual(ctx.get(enc.o), 2)
5050

51-
yield enc.i.eq(0b0110)
52-
self.assertEqual((yield enc.n), 0)
53-
self.assertEqual((yield enc.o), 1)
51+
ctx.set(enc.i, 0b0110)
52+
self.assertEqual(ctx.get(enc.n), 0)
53+
self.assertEqual(ctx.get(enc.o), 1)
5454

5555
sim = Simulator(enc)
56-
sim.add_testbench(process)
56+
sim.add_testbench(testbench)
5757
sim.run()
5858

5959

6060
class DecoderTestCase(FHDLTestCase):
6161
def test_basic(self):
6262
dec = Decoder(4)
63-
def process():
64-
self.assertEqual((yield dec.o), 0b0001)
63+
async def testbench(ctx):
64+
self.assertEqual(ctx.get(dec.o), 0b0001)
6565

66-
yield dec.i.eq(1)
67-
self.assertEqual((yield dec.o), 0b0010)
66+
ctx.set(dec.i, 1)
67+
self.assertEqual(ctx.get(dec.o), 0b0010)
6868

69-
yield dec.i.eq(3)
70-
self.assertEqual((yield dec.o), 0b1000)
69+
ctx.set(dec.i, 3)
70+
self.assertEqual(ctx.get(dec.o), 0b1000)
7171

72-
yield dec.n.eq(1)
73-
self.assertEqual((yield dec.o), 0b0000)
72+
ctx.set(dec.n, 1)
73+
self.assertEqual(ctx.get(dec.o), 0b0000)
7474

7575
sim = Simulator(dec)
76-
sim.add_testbench(process)
76+
sim.add_testbench(testbench)
7777
sim.run()
7878

7979

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