Inline Asm Constraints and Modifiers

We have customers with usecases that want more kinds of register
constraints and modifiers. This change proposes support for these
constraints and modifiers, and their names.

Broadly, these are intended to make it easier for users who want to
manually assemble instructions inside inline assembly blocks, either
using the existing instruction formats, or using the raw form of the
`.insn` directive. This makes it easier for hardware designers to
experiment on new ISA extensions, and makes it easier to support
the use of proprietary extensions with unmodified open-source
toolchains.

There are three groups of additions here:

- Constraints for RVC-compatible registers. These use the `c` prefix on
  an existing register constraint, so `cr` gives a GPR between x8-x15,
  and `cf` does the same for an FPR between f8-f15.

  I'm not aware of compressed vector instructions, but we could add
  `cvr`, `cvd` and `cvm` in the future if the core architecture ends up
  having the concept of a vector register with an RVC encoding.

- A modifier, `N`, to print the raw encoding of a register. This is used
  when using `.insn <length>, <encoding>`, where the user wants to pass
  a value to the instruction in a known register, but where the
  instruction doesn't follow the existing instruction formats, so the
  assembly parser is not expecting a register name, just a raw integer.

- Constraints for even-odd pairs of registers. These use the `P` prefix
  on an existing register constraint. At the moment, this only defines
  `Pr` to mean an even-odd pair of GPRs. (We use `P` as a prefix as `p`
  already means "pointer" in GCC's target-independent constraints).

  I think this will print as the even register in the even-odd register
  pair, but I'm still working on the details around this.

  While the concept of even-odd register pairs is reasonably "new",
  there are places in the architecture where these already exist - the
  doubleword/quad CAS in Zacas, and they are also present in the Zilsd
  specification.

Signed-off-by: Sam Elliott <quic_aelliott@quicinc.com>

Author: lenary

src/c-api.adoc

@@ -746,13 +746,18 @@ statements, including both RISC-V specific and common operand constraints.
 |K                  |5-bit unsigned immediate integer operand     |
 |J                  |Zero integer immediate operand               |
 |s                  |symbol or label reference with a constant offset |
+|cr                 |RVC general purpose register (`x8`-`x15`)  |
+|cf                 |RVC floating point register (`f8`-`f15`)   |
+|Pr                 |Even-odd general purpose register pair     |
 |vr                 |Vector register                    |
 |vd                 |Vector register, excluding v0      |
 |vm                 |Vector register, only v0           |
 |===
 
 NOTE: Immediate value must be a compile-time constant.
 
+NOTE: The `c*` and `P*` constraints are designed to be extensible to more kinds of registers in the future.
+
 === The Difference Between `m` and `A` Constraints
 
 The difference between `m` and `A` is whether the operand can have an offset;
@@ -809,6 +814,7 @@ statements, including both RISC-V specific and common operand modifiers.
 |*Modifiers*       |*Description*                                                                  |*Note*
 |z            |Print `zero` (`x0`) register for immediate 0, typically used with constraints `J` |
 |i            |Print `i` if corresponding operand is immediate.                                  |
+|N            |Print register encoding as integer (0-31). |
 |===
 
 [id=function-multi-version]