Tests: Add t_trace_enum_fst

Author: wsnyder

.github/workflows/build.yml

@@ -20,7 +20,6 @@ jobs:
       CI_OS_NAME: linux
       CI_RUNS_ON: ubuntu-22.04
       CI_COMMIT: ${{ github.sha }}
-      CI_M32: 0
       CCACHE_COMPRESS: 1
       CCACHE_DIR: ${{ github.workspace }}/.ccache
       CCACHE_MAXSIZE: 4Gi

t/t_trace_enum.v

@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2009 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define STRINGIFY(x) `"x`"
+
+typedef enum logic [1:0] {VAL_A, VAL_B, VAL_C, VAL_D} state_t;
+
+interface MyIntf;
+   state_t state;
+endinterface
+
+module t;
+   logic clk;
+   initial forever begin
+      clk = 1;
+      #5;
+      clk = 0;
+      #5;
+   end
+
+   MyIntf #() sink ();
+   state_t v_enumed;
+
+   typedef enum logic [1:0] {VAL_X, VAL_Y, VAL_Z} other_state_t;
+   other_state_t v_other_enumed;
+
+   initial begin
+      $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+      $dumpvars();
+      #100;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

t/t_trace_enum_fst.py

@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_enum.v"
+
+test.compile(verilator_flags2=['--binary --trace-fst'])
+
+test.execute()
+
+test.file_grep(test.obj_dir + "/simx.fst", r'.')
+
+test.passes()