Design Verification Fresher | Verilog, SystemVerilog & Python | UVM | AXI, AHB, APB | ASIC, SOC & RISC-V Enthusiast |
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Fluxray Electronics
- Hormavu, Bengaluru East, Karnatak -560113
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13:56
(UTC +05:30) - karan-nevage.github.io
- @KarankumarNeva1
- @FluxrayElectronics
- ind_karanog
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