Implement an alternative to Recipe (called, say, Sequential) #28
Description
This is a generalization of issue #14. The Recipe semantics is not ideal, in particular variable assignments do not take effect in the same cycle. This makes for Verilog semantics and not C semantics, meaning in particular that Tick is semantically significant even within a sequential piece of code. As a consequence it is not possible to sprinkle Tick around the code for performance improvements or to enable stalling. The Signals have a similar inflexible semantics.
To realize the goal of enabling variable latency interactions (such as cache misses etc) I see no
alternative to designing an alternative to Recipe and migrating all of Reduceron to it.