Skip to content

Commit fd89e9b

Browse files
authored
Fix stm32f103 ADC (#4702)
fix: Fix stm32f103 ADC
1 parent 5a1b885 commit fd89e9b

File tree

3 files changed

+15
-24
lines changed

3 files changed

+15
-24
lines changed

src/machine/machine_stm32_adc_f1.go

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -23,15 +23,6 @@ func InitADC() {
2323
// Enable ADC clock
2424
enableAltFuncClock(unsafe.Pointer(stm32.ADC1))
2525

26-
// set scan mode
27-
stm32.ADC1.CR1.SetBits(stm32.ADC_CR1_SCAN)
28-
29-
// clear CONT, ALIGN, EXTRIG and EXTSEL bits from CR2
30-
stm32.ADC1.CR2.ClearBits(stm32.ADC_CR2_CONT | stm32.ADC_CR2_ALIGN | stm32.ADC_CR2_EXTTRIG_Msk | stm32.ADC_CR2_EXTSEL_Msk)
31-
32-
stm32.ADC1.SQR1.ClearBits(stm32.ADC_SQR1_L_Msk)
33-
stm32.ADC1.SQR1.SetBits(2 << stm32.ADC_SQR1_L_Pos) // 2 means 3 conversions
34-
3526
// enable
3627
stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_ADON)
3728

@@ -61,7 +52,7 @@ func (a ADC) Get() uint16 {
6152
stm32.ADC1.SQR3.SetBits(ch)
6253

6354
// start conversion
64-
stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_SWSTART)
55+
stm32.ADC1.CR2.SetBits(stm32.ADC_CR2_ADON)
6556

6657
// wait for conversion to complete
6758
for !stm32.ADC1.SR.HasBits(stm32.ADC_SR_EOC) {
@@ -70,12 +61,6 @@ func (a ADC) Get() uint16 {
7061
// read result as 16 bit value
7162
result := uint16(stm32.ADC1.DR.Get()) << 4
7263

73-
// clear flag
74-
stm32.ADC1.SR.ClearBits(stm32.ADC_SR_EOC)
75-
76-
// clear rank
77-
stm32.ADC1.SQR3.ClearBits(ch)
78-
7964
return result
8065
}
8166

src/machine/machine_stm32f103.go

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -221,14 +221,19 @@ func (p Pin) enableClock() {
221221

222222
// Enable peripheral clock. Expand to include all the desired peripherals
223223
func enableAltFuncClock(bus unsafe.Pointer) {
224-
if bus == unsafe.Pointer(stm32.USART1) {
224+
switch bus {
225+
case unsafe.Pointer(stm32.USART1):
225226
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_USART1EN)
226-
} else if bus == unsafe.Pointer(stm32.USART2) {
227+
case unsafe.Pointer(stm32.USART2):
227228
stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_USART2EN)
228-
} else if bus == unsafe.Pointer(stm32.I2C1) {
229+
case unsafe.Pointer(stm32.I2C1):
229230
stm32.RCC.APB1ENR.SetBits(stm32.RCC_APB1ENR_I2C1EN)
230-
} else if bus == unsafe.Pointer(stm32.SPI1) {
231+
case unsafe.Pointer(stm32.SPI1):
231232
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_SPI1EN)
233+
case unsafe.Pointer(stm32.ADC1):
234+
stm32.RCC.APB2ENR.SetBits(stm32.RCC_APB2ENR_ADC1EN)
235+
default:
236+
panic("machine: unknown peripheral")
232237
}
233238
}
234239

src/runtime/runtime_stm32f103.go

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -33,10 +33,11 @@ func buffered() int {
3333

3434
// initCLK sets clock to 72MHz using HSE 8MHz crystal w/ PLL X 9 (8MHz x 9 = 72MHz).
3535
func initCLK() {
36-
stm32.FLASH.ACR.SetBits(stm32.FLASH_ACR_LATENCY_WS2) // Two wait states, per datasheet
37-
stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE1_Div2 << stm32.RCC_CFGR_PPRE1_Pos) // prescale PCLK1 = HCLK/2
38-
stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE2_Div1 << stm32.RCC_CFGR_PPRE2_Pos) // prescale PCLK2 = HCLK/1
39-
stm32.RCC.CR.SetBits(stm32.RCC_CR_HSEON) // enable HSE clock
36+
stm32.FLASH.ACR.SetBits(stm32.FLASH_ACR_LATENCY_WS2) // Two wait states, per datasheet
37+
stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE1_Div2 << stm32.RCC_CFGR_PPRE1_Pos) // prescale PCLK1 = HCLK/2
38+
stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_PPRE2_Div1 << stm32.RCC_CFGR_PPRE2_Pos) // prescale PCLK2 = HCLK/1
39+
stm32.RCC.CFGR.SetBits(stm32.RCC_CFGR_ADCPRE_Div6 << stm32.RCC_CFGR_ADCPRE_Pos) // prescale ADCCLK = PCLK2/6
40+
stm32.RCC.CR.SetBits(stm32.RCC_CR_HSEON) // enable HSE clock
4041

4142
// wait for the HSEREADY flag
4243
for !stm32.RCC.CR.HasBits(stm32.RCC_CR_HSERDY) {

0 commit comments

Comments
 (0)