Add sim model of uds_rom to allow linting

Currently it is not possible to lint the UDS core, due to a missing model of the uds_rom.

```
iverilog -Wall -o top.sim ../tb/tb_uds.v ../rtl/uds.v
../rtl/uds.v:53: error: Unknown module type: uds_rom
2 error(s) during elaboration.
*** These modules were missing:
        uds_rom referenced 1 times.
***
make: *** [Makefile:28: top.sim] Error 2
```