VHDL Backend : Missing assignement in AddReduce.vhd ? #54
Description
Hi,
I've started working with this tool. I tried to convert a simple xgboost tree into VHDL. Conifer is creating the files without a problem, however when I try to import them in Vivado it's a mess. After struggling a bit with the library names (it's my first time using VHDL, usually I'm working with Verilog), I decide to go another route and convert the VHDL code into a Verilog module using GHDL (and/or Yosys).
In case someone is curious, that's how I'm currently doing it :
ghdl -a Constants.vhd
ghdl -a Types.vhd
ghdl -a AddReduce.vhd
ghdl -a Arrays0.vhd
ghdl -a Tree.vhd
ghdl -a BDT.vhd
ghdl -a BDTTop.vhd
ghdl --synth --out=verilog bdttop > BDTTop.v
It's seems to be working, and while my VHDL attemps crashed Vivado, the Verilog file plays very nicely.
However I get following warnings :
AddReduce.vhd:28:11:warning: declaration of "addreduce" hides entity "addreduce" [-Whide]
component AddReduce is
^
AddReduce.vhd:59:10:warning: no assignment for offsets 0:17 of signal "dint"
signal dInt : tyArray(0 to intLen - 1) := (others => (others => '0'));
^
AddReduce.vhd:59:10:warning: no assignment for offsets 0:17 of signal "dint"
signal dInt : tyArray(0 to intLen - 1) := (others => (others => '0'));
And indeed, when I try to run a simulation with Vivado I find that the output signal from the tree is 'XXXXXXXX', and I have some internal ZZZs .
Is this an issue from your side, or did something go wrong during the translation process ?
(I'm using Vivado 2020.1)