From ecc28fac95fcb68d7cad68c70975d39e55a4b1d6 Mon Sep 17 00:00:00 2001 From: Takeshi Yoneda Date: Tue, 21 May 2024 14:20:00 +0900 Subject: [PATCH 1/2] regalloc: removes map use for less memory pressure Signed-off-by: Takeshi Yoneda --- internal/engine/wazevo/backend/regalloc/regalloc.go | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/internal/engine/wazevo/backend/regalloc/regalloc.go b/internal/engine/wazevo/backend/regalloc/regalloc.go index b4450d56fb..8e1f1e4811 100644 --- a/internal/engine/wazevo/backend/regalloc/regalloc.go +++ b/internal/engine/wazevo/backend/regalloc/regalloc.go @@ -974,13 +974,6 @@ func (a *Allocator) fixMergeState(f Function, blk Block) { bID := blk.ID() blkSt := a.getOrAllocateBlockState(bID) desiredOccupants := &blkSt.startRegs - aliveOnRegVRegs := make(map[VReg]RealReg) - for i := 0; i < 64; i++ { - r := RealReg(i) - if v := blkSt.startRegs.get(r); v.Valid() { - aliveOnRegVRegs[v] = r - } - } if wazevoapi.RegAllocLoggingEnabled { fmt.Println("fixMergeState", blk.ID(), ":", desiredOccupants.format(a.regInfo)) @@ -1002,7 +995,7 @@ func (a *Allocator) fixMergeState(f Function, blk Block) { for ii := 0; ii < 64; ii++ { r := RealReg(ii) if v := predSt.endRegs.get(r); v.Valid() { - if _, ok := aliveOnRegVRegs[v]; !ok { + if _v := blkSt.startRegs.get(r); !_v.Valid() { continue } currentOccupants.add(r, v) From 9d77b6a4a0a9c36a3896be1b96329126333b3c77 Mon Sep 17 00:00:00 2001 From: Takeshi Yoneda Date: Tue, 21 May 2024 14:29:33 +0900 Subject: [PATCH 2/2] regalloc: simplifies the for loop over possible Real regs Signed-off-by: Takeshi Yoneda --- internal/engine/wazevo/backend/regalloc/regalloc.go | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/internal/engine/wazevo/backend/regalloc/regalloc.go b/internal/engine/wazevo/backend/regalloc/regalloc.go index 8e1f1e4811..3cb04aa8cc 100644 --- a/internal/engine/wazevo/backend/regalloc/regalloc.go +++ b/internal/engine/wazevo/backend/regalloc/regalloc.go @@ -944,8 +944,7 @@ func (a *Allocator) allocBlock(f Function, blk Block) { func (a *Allocator) releaseCallerSavedRegs(addrReg RealReg) { s := &a.state - for i := 0; i < 64; i++ { - allocated := RealReg(i) + for allocated := RealReg(0); allocated < 64; allocated++ { if allocated == addrReg { // If this is the call indirect, we should not touch the addr register. continue } @@ -992,8 +991,7 @@ func (a *Allocator) fixMergeState(f Function, blk Block) { currentOccupantsRev := make(map[VReg]RealReg) pred := blk.Pred(i) predSt := a.getOrAllocateBlockState(pred.ID()) - for ii := 0; ii < 64; ii++ { - r := RealReg(ii) + for r := RealReg(0); r < 64; r++ { if v := predSt.endRegs.get(r); v.Valid() { if _v := blkSt.startRegs.get(r); !_v.Valid() { continue @@ -1022,8 +1020,7 @@ func (a *Allocator) fixMergeState(f Function, blk Block) { fmt.Println("\t", pred.ID(), ":", currentOccupants.format(a.regInfo)) } - for ii := 0; ii < 64; ii++ { - r := RealReg(ii) + for r := RealReg(0); r < 64; r++ { desiredVReg := desiredOccupants.get(r) if !desiredVReg.Valid() { continue @@ -1162,8 +1159,7 @@ func (a *Allocator) scheduleSpill(f Function, vs *vrState) { } for pos != definingBlk { st := a.getOrAllocateBlockState(pos.ID()) - for ii := 0; ii < 64; ii++ { - rr := RealReg(ii) + for rr := RealReg(0); rr < 64; rr++ { if st.startRegs.get(rr) == v { r = rr // Already in the register, so we can place the spill at the beginning of the block.